style: eliminating DontCare (#27)

* style: eliminating DontCare

* style: further eliminate DontCare

src/main/scala/coupledL2/AcquireUnit.scala

@@ -80,7 +80,7 @@ class AcquireUnit(implicit p: Parameters) extends L2Module {
   a_acquire.bits.source := task.source
   a_acquire.bits.address := Cat(task.tag, task.set, 0.U(offsetBits.W))
   a_acquire.bits.mask := Fill(edgeOut.manager.beatBytes, 1.U(1.W))
-  a_acquire.bits.data := DontCare
+  a_acquire.bits.data := 0.U((edgeOut.manager.beatBytes * 8).W)
   a_acquire.bits.echo.lift(DirtyKey).foreach(_ := true.B)
   a_acquire.bits.user.lift(PreferCacheKey).foreach(_ := false.B)
   a_acquire.bits.user.lift(utility.ReqSourceKey).foreach(_ := task.reqSource)

src/main/scala/coupledL2/CoupledL2.scala

@@ -152,14 +152,6 @@ trait HasCoupledL2Parameters {
   }
 }
 
-trait DontCareInnerLogic { this: Module =>
-  override def IO[T <: Data](iodef: T): T = {
-    val p = chisel3.experimental.IO.apply(iodef)
-    p <> DontCare
-    p
-  }
-}
-
 class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Parameters {
 
   val xfer = TransferSizes(blockBytes, blockBytes)
@@ -276,8 +268,8 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
         prefetcher.get.io.recv_addr.bits := x.in.head._1.addr
         prefetcher.get.io_l2_pf_en := x.in.head._1.l2_pf_en
       case None =>
-        prefetcher.foreach(_.io.recv_addr := DontCare)
-        prefetcher.foreach(_.io_l2_pf_en := DontCare)
+        prefetcher.foreach(_.io.recv_addr := 0.U.asTypeOf(ValidIO(UInt(64.W))))
+        prefetcher.foreach(_.io_l2_pf_en := false.B)
     }
 
     def restoreAddress(x: UInt, idx: Int) = {

src/main/scala/coupledL2/DataStorage.scala

@@ -37,7 +37,7 @@ class DSBlock(implicit p: Parameters) extends L2Bundle {
   val data = UInt((blockBytes * 8).W)
 }
 
-class DataStorage(implicit p: Parameters) extends L2Module with DontCareInnerLogic {
+class DataStorage(implicit p: Parameters) extends L2Module {
   val io = IO(new Bundle() {
     // there is only 1 read or write request in the same cycle,
     // so only 1 req port is necessary
@@ -53,9 +53,6 @@ class DataStorage(implicit p: Parameters) extends L2Module with DontCareInnerLog
     singlePort = true 
   ))
 
-  array.io.r <> DontCare
-  array.io.w <> DontCare
-
   val arrayIdx = Cat(io.req.bits.way, io.req.bits.set)
   val wen = io.req.valid && io.req.bits.wen
   val ren = io.req.valid && !io.req.bits.wen

src/main/scala/coupledL2/Directory.scala

@@ -86,7 +86,7 @@ class TagWrite(implicit p: Parameters) extends L2Bundle {
   val wtag = UInt(tagBits.W)
 }
 
-class Directory(implicit p: Parameters) extends L2Module with DontCareInnerLogic {
+class Directory(implicit p: Parameters) extends L2Module {
 
   val io = IO(new Bundle() {
     val read = Flipped(DecoupledIO(new DirRead))
@@ -119,11 +119,6 @@ class Directory(implicit p: Parameters) extends L2Module with DontCareInnerLogic
   val resetFinish = RegInit(false.B)
   val resetIdx = RegInit((sets - 1).U)
 
-  tagArray.io.r <> DontCare
-  tagArray.io.w <> DontCare
-  metaArray.io.r <> DontCare
-  metaArray.io.w <> DontCare
-
   // Tag R/W
   tagRead := tagArray.io.r(io.read.fire, io.read.bits.set).resp.data
   tagArray.io.w(

src/main/scala/coupledL2/GrantBuffer.scala

@@ -58,9 +58,6 @@ abstract class BaseGrantBuffer(implicit p: Parameters) extends L2Module {
     val prefetchResp = prefetchOpt.map(_ => DecoupledIO(new PrefetchResp))
     val grantStatus  = Output(Vec(sourceIdAll, new GrantStatus))
   })
-
-  io.l1Hint := DontCare
-  io.globalCounter := DontCare
 }
 
 // Communicate with L1
@@ -138,7 +135,6 @@ class GrantBuffer(implicit p: Parameters) extends BaseGrantBuffer {
 
   def toTLBundleD(task: TaskBundle, data: UInt = 0.U) = {
     val d = Wire(new TLBundleD(edgeIn.bundle))
-    d := DontCare
     d.opcode := task.opcode
     d.param := task.param
     d.size := offsetBits.U
@@ -205,12 +201,13 @@ class GrantBuffer(implicit p: Parameters) extends BaseGrantBuffer {
   assert(!io.d_task.valid || io.d_task.ready) 
 
   io.e.ready := true.B
-  io.e_resp := DontCare
   io.e_resp.valid := io.e.valid
   io.e_resp.mshrId := io.e.bits.sink
-  io.e_resp.respInfo := DontCare
   io.e_resp.respInfo.opcode := GrantAck
+  io.e_resp.respInfo.param := 0.U(3.W)
   io.e_resp.respInfo.last := true.B
+  io.e_resp.respInfo.dirty := false.B
+  io.e_resp.respInfo.isHit := false.B
 
   if (cacheParams.enablePerf) {
     XSPerfAccumulate(cacheParams, "grant_buffer_full", full)

src/main/scala/coupledL2/GrantBufferFIFO.scala

@@ -157,7 +157,6 @@ class GrantBufferFIFO(implicit p: Parameters) extends BaseGrantBuffer with HasCi
 
   def toTLBundleD(task: TaskBundle, data: UInt = 0.U) = {
     val d = Wire(new TLBundleD(edgeIn.bundle))
-    d := DontCare
     d.opcode := task.opcode
     d.param := task.param
     d.size := offsetBits.U
@@ -181,7 +180,8 @@ class GrantBufferFIFO(implicit p: Parameters) extends BaseGrantBuffer with HasCi
     (next_beat, next_beatsOH)
   }
 
-  io.d := DontCare
+  io.d.valid := false.B
+  io.d.bits := 0.U.asTypeOf(io.d.bits)
   for(idx <- (0 until mshrsAll)) {
     when(deqPtr === idx.U) {
       io.d.valid := block_valids(idx) && tasks(idx).opcode =/= HintAck // L1 does not need HintAck (for now)
@@ -234,12 +234,15 @@ class GrantBufferFIFO(implicit p: Parameters) extends BaseGrantBuffer with HasCi
   }
 
   io.e.ready := true.B
-  io.e_resp := DontCare
   io.e_resp.valid := io.e.valid
   io.e_resp.mshrId := io.e.bits.sink
-  io.e_resp.respInfo := DontCare
+  io.e_resp.set := 0.U(setBits.W)
+  io.e_resp.tag := 0.U(tagBits.W)
   io.e_resp.respInfo.opcode := GrantAck
+  io.e_resp.respInfo.param := 0.U(3.W)
   io.e_resp.respInfo.last := true.B
+  io.e_resp.respInfo.dirty := false.B
+  io.e_resp.respInfo.isHit := false.B
 
   if (cacheParams.enablePerf) {
     XSPerfAccumulate(cacheParams, "grant_buffer_full", full)

src/main/scala/coupledL2/MSHR.scala

@@ -130,7 +130,6 @@ class MSHR(implicit p: Parameters) extends L2Module {
 
   val a_task = {
     val oa = io.tasks.source_a.bits
-    oa := DontCare
     oa.tag := req.tag
     oa.set := req.set
     oa.off := req.off
@@ -154,7 +153,6 @@ class MSHR(implicit p: Parameters) extends L2Module {
 
   val b_task = {
     val ob = io.tasks.source_b.bits
-    ob := DontCare
     ob.tag := dirResult.tag
     ob.set := dirResult.set
     ob.off := 0.U
@@ -174,7 +172,6 @@ class MSHR(implicit p: Parameters) extends L2Module {
   }
   val mp_release, mp_probeack, mp_grant = Wire(new TaskBundle)
   val mp_release_task = {
-    mp_release := DontCare
     mp_release.channel := req.channel
     mp_release.tag := dirResult.tag
     mp_release.set := req.set
@@ -192,25 +189,34 @@ class MSHR(implicit p: Parameters) extends L2Module {
       }
     }
     mp_release.param := Mux(isT(meta.state), TtoN, BtoN)
+    mp_release.size := 0.U(msgSizeBits.W)
+    mp_release.sourceId := 0.U(sourceIdBits.W)
+    mp_release.bufIdx := 0.U(bufIdxBits.W)
+    mp_release.needProbeAckData := false.B
     mp_release.mshrTask := true.B
     mp_release.mshrId := io.id
     mp_release.aliasTask.foreach(_ := false.B)
     mp_release.useProbeData := true.B // read ReleaseBuf when useProbeData && opcode(0) is true
+    mp_release.pbIdx := 0.U(mshrBits.W)
+    mp_release.fromL2pft.foreach(_ := false.B)
+    mp_release.needHint.foreach(_ := false.B)
     mp_release.way := req.way
     mp_release.dirty := meta.dirty && meta.state =/= INVALID || probeDirty
     mp_release.metaWen := true.B
     mp_release.meta := MetaEntry()
     mp_release.tagWen := false.B
     mp_release.dsWen := false.B
+    mp_release.wayMask := 0.U(cacheParams.ways.W)
+    mp_release.reqSource := 0.U(MemReqSource.reqSourceBits.W)
     mp_release
   }
 
   val mp_probeack_task = {
-    mp_probeack := DontCare
     mp_probeack.channel := req.channel
     mp_probeack.tag := req.tag
     mp_probeack.set := req.set
     mp_probeack.off := req.off
+    mp_probeack.alias.foreach(_ := 0.U)
     mp_probeack.opcode := Mux(
       meta.dirty && isT(meta.state) || probeDirty || req.needProbeAckData,
       ProbeAckData,
@@ -225,10 +231,17 @@ class MSHR(implicit p: Parameters) extends L2Module {
         Cat(true.B, toB) -> TtoB
       )
     )
+    mp_probeack.size := 0.U(msgSizeBits.W)
+    mp_probeack.sourceId := 0.U(sourceIdBits.W)
+    mp_probeack.bufIdx := 0.U(bufIdxBits.W)
+    mp_probeack.needProbeAckData := false.B
     mp_probeack.mshrTask := true.B
     mp_probeack.mshrId := io.id
     mp_probeack.aliasTask.foreach(_ := false.B)
     mp_probeack.useProbeData := true.B // read ReleaseBuf when useProbeData && opcode(0) is true
+    mp_probeack.pbIdx := 0.U(mshrBits.W)
+    mp_probeack.fromL2pft.foreach(_ := false.B)
+    mp_probeack.needHint.foreach(_ := false.B)
     mp_probeack.way := req.way
     mp_probeack.dirty := meta.dirty && meta.state =/= INVALID || probeDirty
     mp_probeack.meta := MetaEntry(
@@ -250,15 +263,17 @@ class MSHR(implicit p: Parameters) extends L2Module {
     mp_probeack.metaWen := true.B
     mp_probeack.tagWen := false.B
     mp_probeack.dsWen := req.param =/= toN && probeDirty
+    mp_probeack.wayMask := 0.U(cacheParams.ways.W)
+    mp_probeack.reqSource := 0.U(MemReqSource.reqSourceBits.W)
     mp_probeack
   }
 
   val mp_grant_task    = {
-    mp_grant := DontCare
     mp_grant.channel := req.channel
     mp_grant.tag := req.tag
     mp_grant.set := req.set
     mp_grant.off := req.off
+    mp_grant.alias.foreach(_ := 0.U)
     mp_grant.sourceId := req.source
     mp_grant.opcode := odOpGen(req.opcode)
     mp_grant.param := Mux(
@@ -274,8 +289,12 @@ class MSHR(implicit p: Parameters) extends L2Module {
         )
       )
     )
+    mp_grant.size := 0.U(msgSizeBits.W)
+    mp_grant.bufIdx := 0.U(bufIdxBits.W)
+    mp_grant.needProbeAckData := false.B
     mp_grant.mshrTask := true.B
     mp_grant.mshrId := io.id
+    mp_grant.aliasTask.foreach(_ := false.B)
     mp_grant.way := req.way
     // if it is a Get or Prefetch, then we must keep alias bits unchanged
     // in case future probes gets the wrong alias bits
@@ -285,6 +304,8 @@ class MSHR(implicit p: Parameters) extends L2Module {
     // [Alias] write probeData into DS for alias-caused Probe,
     // but not replacement-cased Probe
     mp_grant.useProbeData := dirResult.hit && req_get || req.aliasTask.getOrElse(false.B)
+    mp_grant.pbIdx := 0.U(mshrBits.W)
+    mp_grant.dirty := false.B
 
     mp_grant.meta := MetaEntry(
       dirty = gotDirty || dirResult.hit && (meta.dirty || probeDirty),
@@ -315,6 +336,8 @@ class MSHR(implicit p: Parameters) extends L2Module {
     mp_grant.dsWen := !dirResult.hit && !req_put && gotGrantData || probeDirty && (req_get || req.aliasTask.getOrElse(false.B))
     mp_grant.fromL2pft.foreach(_ := req.fromL2pft.get)
     mp_grant.needHint.foreach(_ := false.B)
+    mp_grant.wayMask := 0.U(cacheParams.ways.W)
+    mp_grant.reqSource := 0.U(MemReqSource.reqSourceBits.W)
     mp_grant
   }
   io.tasks.mainpipe.bits := ParallelPriorityMux(

src/main/scala/coupledL2/MainPipe.scala

@@ -190,7 +190,6 @@ class MainPipe(implicit p: Parameters) extends L2Module {
   // Allocation of MSHR: new request only
   val alloc_state = WireInit(0.U.asTypeOf(new FSMState()))
   alloc_state.elements.foreach(_._2 := true.B)
-  io.toMSHRCtl.mshr_alloc_s3 := DontCare
   io.toMSHRCtl.mshr_alloc_s3.valid := task_s3.valid && !mshr_req_s3 && need_mshr_s3
   io.toMSHRCtl.mshr_alloc_s3.bits.dirResult := dirResult_s3
   io.toMSHRCtl.mshr_alloc_s3.bits.state := alloc_state
@@ -205,13 +204,22 @@ class MainPipe(implicit p: Parameters) extends L2Module {
   ms_task.param            := req_s3.param
   ms_task.size             := req_s3.size
   ms_task.sourceId         := req_s3.sourceId
+  ms_task.bufIdx           := 0.U(bufIdxBits.W)
   ms_task.needProbeAckData := req_s3.needProbeAckData
+  ms_task.mshrTask         := false.B
+  ms_task.mshrId           := 0.U(mshrBits.W)
   ms_task.aliasTask.foreach(_ := cache_alias)
   ms_task.useProbeData     := false.B
   ms_task.pbIdx            := req_s3.pbIdx
   ms_task.fromL2pft.foreach(_ := req_s3.fromL2pft.get)
   ms_task.needHint.foreach(_  := req_s3.needHint.get)
+  ms_task.dirty            := false.B
   ms_task.way              := dirResult_s3.way
+  ms_task.meta             := 0.U.asTypeOf(new MetaEntry)
+  ms_task.metaWen          := false.B
+  ms_task.tagWen           := false.B
+  ms_task.dsWen            := false.B
+  ms_task.wayMask          := 0.U(cacheParams.ways.W)
   ms_task.reqSource        := req_s3.reqSource
 
   /* ======== Resps to SinkA/B/C Reqs ======== */

src/main/scala/coupledL2/RefillUnit.scala

@@ -60,8 +60,8 @@ class RefillUnit(implicit p: Parameters) extends L2Module {
 
   io.resp.valid := (first || last) && io.sinkD.valid
   io.resp.mshrId := io.sinkD.bits.source
-  io.resp.set := DontCare
-  io.resp.tag := DontCare
+  io.resp.set := 0.U(setBits.W)
+  io.resp.tag := 0.U(tagBits.W)
   io.resp.respInfo.opcode := io.sinkD.bits.opcode
   io.resp.respInfo.param := io.sinkD.bits.param
   io.resp.respInfo.last := last

src/main/scala/coupledL2/RequestArb.scala

@@ -87,7 +87,6 @@ class RequestArb(implicit p: Parameters) extends L2Module {
   /* Task generation and pipelining */
   def fromTLBtoTaskBundle(b: TLBundleB): TaskBundle = {
     val task = Wire(new TaskBundle)
-    task := DontCare
     task.channel := "b010".U
     task.tag := parseAddress(b.address)._1
     task.set := parseAddress(b.address)._2
@@ -96,10 +95,22 @@ class RequestArb(implicit p: Parameters) extends L2Module {
     task.opcode := b.opcode
     task.param := b.param
     task.size := b.size
+    task.sourceId := 0.U(sourceIdBits.W)
+    task.bufIdx := 0.U(bufIdxBits.W)
     task.needProbeAckData := b.data(0) // TODO: parameterize this
     task.mshrTask := false.B
+    task.mshrId := 0.U(mshrBits.W)
+    task.aliasTask.foreach(_ := false.B)
+    task.useProbeData := false.B
+    task.pbIdx := 0.U(mshrBits.W)
     task.fromL2pft.foreach(_ := false.B)
     task.needHint.foreach(_ := false.B)
+    task.dirty := false.B
+    task.way := 0.U(wayBits.W)
+    task.meta := 0.U.asTypeOf(new MetaEntry)
+    task.metaWen := false.B
+    task.tagWen := false.B
+    task.dsWen := false.B
     task.wayMask := Fill(cacheParams.ways, "b1".U)
     task.reqSource := MemReqSource.NoWhere.id.U // Ignore
     task