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@markaulunGH markaulunGH commented Oct 26, 2024

  1. Fixed the bug where the SRAM's CE signal was active when the reset signal was active.
  2. Fixed the bug where the Queue still allowed entries when reset or flush was active, causing the IFU to continue fetching instructions while reset was active.

Waveform diagram for issue:
WAVE
The BTB SRAM chip select signal is active when the reset signal is active, but there is no initialization operation at this time. The initialization of the BTB SRAM occurs after the reset signal is deasserted.
WAVE2

Commonality between the two issues: Both involve the Queue signal or SRAM chip select signal being active while the reset signal is active.
Resetting:Queue io.enq.ready is 1 => IFU io.imem.req.valid is 1 => Cache SRAM's CE is 1(valid)
Resetting: _resetState is 1 => BTB SRAM's CE is 1 (Valid) (before the initialization of the BTB SRAM)

Simulation results after code modification

  1. The SRAM chip select signal is not active when the reset signal is active.
  2. Can run the simulation of NutShell's built-in linux.bin with difftest enabled without encountering any errors.
    command:./build/emu -b 0 -e 0 -i ./ready-to-run/linux.bin -C 200000000 --diff ./ready-to-run/riscv64-nemu-interpreter-so

poemonsense and others added 2 commits October 26, 2024 16:43
NutShell master branch re-adaption for FPGA platforms
…sh was active, causing the IFU to continue fetching instructions while reset was active.
@markaulunGH markaulunGH reopened this Oct 30, 2024
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3 participants