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add rk3588 support #7056

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add rk3588 support #7056

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19 changes: 19 additions & 0 deletions core/arch/arm/plat-rockchip/platform_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,25 @@
#define FIREWALL_DDR_BASE 0xff534000
#define FIREWALL_DDR_SIZE SIZE_K(16)

#elif defined(PLATFORM_FLAVOR_rk3588)
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Having a SoC as the name of the flavor is not a good idea IMO. How would you name different boards using the same SoC? Although yes, ideally if we use DT and runtime detection etc. it may be possible but it doesn't seem to apply here.


#define GIC_BASE 0xFE600000
#define GIC_SIZE SIZE_K(64)
#define GICD_BASE GIC_BASE
#define GICC_BASE 0

#define UART1_BASE 0xfeb40000
#define UART1_SIZE SIZE_K(64)

#define UART2_BASE 0xfeb50000
#define UART2_SIZE SIZE_K(64)

#define UART5_BASE 0xfeb80000
#define UART5_SIZE SIZE_K(64)

#define FIREWALL_DDR_BASE 0xfe030000
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I see rk3588 has two firewalls: FIREWALL_DDR with base address 0xFE030000 and FIREWALL_SYSMEM with base address 0xFE038000 have you been able to find out the difference? I guess the FIREWALL_DDR hold MMU registers, and FIREWALL_SYSMEM holds SMMU registers, but I cannot confirm this.

#define FIREWALL_DDR_SIZE SIZE_K(32)

#else
#error "Unknown platform flavor"
#endif
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52 changes: 52 additions & 0 deletions core/arch/arm/plat-rockchip/platform_rk3588.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,52 @@
// SPDX-License-Identifier: BSD-2-Clause
/*
* Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH
*/

#include <common.h>
#include <io.h>
#include <kernel/panic.h>
#include <mm/core_memprot.h>
#include <platform.h>
#include <platform_config.h>

#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
#define FIREWALL_DDR_FW_DDR_MST_NUM 6

#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))

register_phys_mem_pgdir(MEM_AREA_IO_SEC, FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE);

int platform_secure_ddr_region(int rgn, paddr_t st, size_t sz)
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How have you been able to find out how to set MMU configuration for this SoC? I cannot find any exact MMU register mappings in SoC's TRM.

{
vaddr_t fw_base = (vaddr_t)phys_to_virt_io(FIREWALL_DDR_BASE,
FIREWALL_DDR_SIZE);
paddr_t ed = st + sz;
uint32_t st_mb = st / SIZE_M(1);
uint32_t ed_mb = ed / SIZE_M(1);

if (!fw_base)
panic();

assert(rgn <= 7);
assert(st < ed);

/* Check aligned 1MB */
assert(st % SIZE_M(1) == 0);
assert(ed % SIZE_M(1) == 0);

DMSG("protecting region %d: 0x%lx-0x%lx", rgn, st, ed);

/* Map top and base */
io_write32(fw_base + FIREWALL_DDR_FW_DDR_RGN(rgn),
RG_MAP_SECURE(ed_mb, st_mb));

/* Enable secure setting */
io_setbits32(fw_base + FIREWALL_DDR_FW_DDR_CON_REG, BIT(rgn));

return 0;
}

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