Name		Name	Last commit message	Last commit date
Latest commit History 42 Commits
Arch Diags		Arch Diags
CUDA Cores		CUDA Cores
TensorCoreAmpere		TensorCoreAmpere
TensorCoreHopper		TensorCoreHopper
TensorCoreVolta		TensorCoreVolta
TensorProcessingUnit		TensorProcessingUnit
ImpLinks.md		ImpLinks.md
LICENSE		LICENSE
README.md		README.md

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TheTensorCoreProject

Microarchitecture implementation of my interpretation of Nvidia's SIMT CUDA and Hybrid-Precision Tensor Cores, and Google's Systolic Array TPU MXU

Tensor Core Versions

TensorCore v0: Volta Architecture [FP16MUL FP32ADD]

Volta Tensor Core Architecture Diagram

Volta Tensor Core Architecture Diagram

TensorCore v1: Ampere Architecture [TF32MUL FP32ADD / BF16MUL FP32ADD] + Fine-Grained Structured Sparsity

Ampere Tensor Core Architecture Diagram

Ampere Tensor Core Architecture Diagram

TensorCore v2: Hopper Architecture [FP8(E5M2/E4M3)MUL FP16ADD]

Hopper Tensor Core Architecture Diagram

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Microarchitecture implementation of Nvidia's Tensor Cores

cuda gpgpu floating-point sparse-matrix tpu tensorcore systolic-arrays hybrid-precision-training

BSD-3-Clause license

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