Improving LLVM tests

clang/test/CodeGen/sanitize-coverage-old-pm.c

@@ -6,10 +6,9 @@
 // RUN: %clang %s -target x86_64-unknown-linux-gnu -emit-llvm -S -fsanitize=undefined  -fsanitize-coverage=trace-pc,trace-cmp -o - -flegacy-pass-manager | FileCheck %s --check-prefixes=CHECK,UBSAN
 //
 // Host armv7 is currently unsupported: https://bugs.llvm.org/show_bug.cgi?id=46117
-// UNSUPPORTED: armv7, armv7l, thumbv7, armv8l
+// UNSUPPORTED: armv7, armv7l, thumbv7, armv8l, nanomips
 // The same issue also occurs on a riscv32 host.
-// XFAIL: riscv32, nanomips
->>>>>>> 2c4958ebdae8 (Disable sanitize-coverage-old-pm.c for nanoMIPS)
+// XFAIL: riscv32
 
 int x[10];
 

clang/test/Modules/ExtDebugInfo.cpp

@@ -1,5 +1,3 @@
-// No object emitter on nanomips
-// UNSUPPORTED: nanomips
 // RUN: rm -rf %t
 // Test that only forward declarations are emitted for types defined in modules.
 

llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

@@ -625,13 +625,14 @@ void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
                                      MachineBasicBlock::iterator I) const {
   MipsABIInfo ABI = Subtarget.getABI();
   DebugLoc DL;
-  if (I != MBB.end()) DL = I->getDebugLoc();
+  bool IsNanoMips = Subtarget.hasNanoMips();
+  if ((I != MBB.end()) && IsNanoMips)
+    DL = I->getDebugLoc();
   unsigned ADDiu = ABI.GetPtrAddiuOp();
 
   if (Amount == 0)
     return;
 
-  bool IsNanoMips = Subtarget.hasNanoMips();
   if ((isInt<16>(Amount) && !IsNanoMips) || (isInt<32>(Amount) && IsNanoMips)) {
     // addi sp, sp, amount
     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);

llvm/lib/Target/Mips/NanoMipsInstrInfo.td

@@ -358,6 +358,11 @@ def XORI_NM  : ArithLogicI32<"xori", uimm12_nm, GPR32NMOpnd, imm32ZExt12, xor>;
 def ANDI_NM  : ArithLogicI32<"andi", uimm16, GPR32NMOpnd, imm32ZExt12ANDI, and>;
 def SLTI_NM  : ArithLogicI32<"slti", uimm12_nm, GPR32NMOpnd, imm32ZExt12, setlt>;
 def SLTIU_NM : ArithLogicI32<"sltiu", uimm12_nm, GPR32NMOpnd, imm32ZExt12, setult>;
+
+// TODO: isCodeGenOnly=1 was added to avoid conflicts with same instructions
+//       for other Mips targets. Handle this when adding integrated asm
+//       for NanoMips.
+let isCodeGenOnly = 1 in
 def SEQI_NM  : ArithLogicI32<"seqi", uimm12_nm, GPR32NMOpnd, imm32ZExt12, seteq>;
 
 // P.SHIFT pool of instructions
@@ -369,12 +374,13 @@ def ROTR_NM : ArithLogicI32<"rotr", uimm5_nm, GPR32NMOpnd, imm32ZExt5, rotr>;
 def EXT_NM : ExtBaseNM;
 def INS_NM : InsBaseNM;
 
+let isCodeGenOnly = 1 in
 def ADDiu_NM : ArithLogicI32<"addiu", uimm16_simm12, GPR32NMOpnd,
                              imm32SExt12OrZExt16, add>;
 let Constraints = "$rt = $rs" in
 def ADDIU48_NM : ArithLogicINM<"addiu[48]", simm32_relaxed, GPR32NMOpnd,
                                imm32_NM, add>, InstSize48;
-
+let isCodeGenOnly = 1 in
 def LSA_NM : LoadScaledAddressNM<"lsa", GPR32NMOpnd>;
 
 def SEB_NM : SignExtInRegNM<"seb", i8, GPR32NMOpnd>;
@@ -391,9 +397,11 @@ def TEQ_NM : Trap<"teq">;
 def TNE_NM : Trap<"tne">;
 
 def NOT_NM   : ArithLogicR16<"not", GPR3Opnd, not>;
-def XOR16_NM : ArithLogicR16<"xor16", GPR3Opnd>;
-def AND16_NM : ArithLogicR16<"and16", GPR3Opnd>;
-def OR16_NM  : ArithLogicR16<"or16", GPR3Opnd>;
+let isCodeGenOnly = 1 in {
+  def XOR16_NM : ArithLogicR16<"xor16", GPR3Opnd>;
+  def AND16_NM : ArithLogicR16<"and16", GPR3Opnd>;
+  def OR16_NM  : ArithLogicR16<"or16", GPR3Opnd>;
+}
 
 def JRC_NM : IndirectBranchNM<"jrc", GPR32NMOpnd>;
 
@@ -408,6 +416,7 @@ def BALC_NM : CallNM<"balc", MipsJmpLink, tglobaladdr>, InstSize32;
 def MOVEBALC_NM : MoveBalcBase;
 
 let isReMaterializable = 1 in {
+let isCodeGenOnly = 1 in
 def Li_NM : RegImmNM<"li", simm32_relaxed, GPR32NMOpnd>, InstSize48;
 def LA_NM : RegImmNM<"la", simm32_relaxed, GPR32NMOpnd>, InstSize48;
 

llvm/test/CodeGen/Mips/nanomips/bittestbranch.ll

@@ -1,8 +1,12 @@
 ; RUN: llc -mtriple=nanomips -stop-after=finalize-isel < %s | FileCheck %s
 
+; NOTE: Internal linkage type for all functions in this test was
+;       removed. Otherwise, this test will not pass due to the
+;       problems caused by registration of the NanoMips target.
+
 ; Check correct use of bittest branches
 ; CHECK-LABEL: name:{{.*}}f16
-define internal i32 @f16(i32 %x) {
+define i32 @f16(i32 %x) {
   %and = and i32 %x, 16
   %masked = icmp ne i32 %and, 0
 ; CHECK: BBNEZC_NM {{.*}}, 4, %[[ret1:[0-9a-z\.]+]]
@@ -20,7 +24,7 @@ a:
 }
 
 ; CHECK-LABEL: name:{{.*}}f16eq
-define internal i32 @f16eq(i32 %x) {
+define i32 @f16eq(i32 %x) {
   %and = and i32 %x, 16
   %masked = icmp eq i32 %and, 0
   br i1 %masked, label %a, label %b
@@ -41,7 +45,7 @@ a:
 
 ; Check that bit tests are definitely not used for non-power-of-two ANDs.
 ; CHECK-LABEL: name:{{.*}}f17
-define internal i32 @f17(i32 %x) {
+define i32 @f17(i32 %x) {
   %and = and i32 %x, 17
   %masked = icmp ne i32 %and, 0
 ; CHECK-NOT: BBNEZC_NM
@@ -57,7 +61,7 @@ a:
 }
 
 ; CHECK-LABEL: name:{{.*}}f17eq
-define internal i32 @f17eq(i32 %x) {
+define i32 @f17eq(i32 %x) {
   %and = and i32 %x, 17  %masked = icmp eq i32 %and, 0
   br i1 %masked, label %a, label %b
 ; CHECK-NOT: BBEQZC_NM

llvm/test/CodeGen/Mips/nanomips/jumptable.ll

@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=nanomips -asm-show-inst -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=nanomips -mattr=disable-jump-table-opt -asm-show-inst -verify-machineinstrs < %s | FileCheck %s
 
 define i32 @test_jumptable(i32 %in) {
   switch i32 %in, label %def [
@@ -8,11 +8,11 @@ define i32 @test_jumptable(i32 %in) {
     i32 4, label %lbl4
   ]
 
-; CHECK: li $a1
-; CHECK: Li_NM
+; CHECK: la $a1
+; CHECK: LA_NM
 ; CHECK: lwxs $a0, $a0($a1)
 ; CHECK: LWXS_NM
-; CHECK: jrc $a0
+; CHECK: jrc $ra
 ; CHECK: JRC_NM
 
 def:

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll

@@ -1,6 +1,4 @@
 ; RUN: llc -enable-machine-outliner -mtriple=mips-unknown-linux < %s | FileCheck %s
-;
-; NOTE: Machine outliner doesn't run.
 @x = global i32 0, align 4
 
 define dso_local i32 @check_boundaries() #0 {

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll.generated.expected

@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
 ; RUN: llc -enable-machine-outliner -mtriple=mips-unknown-linux < %s | FileCheck %s
-; NOTE: Machine outliner doesn't run.
 @x = global i32 0, align 4
 
 define dso_local i32 @check_boundaries() #0 {
@@ -87,33 +86,14 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
 ; CHECK-NEXT:    j $BB0_5
 ; CHECK-NEXT:    sw $1, 8($fp)
 ; CHECK-NEXT:  $BB0_3:
-; CHECK-NEXT:    addiu $1, $zero, 2
-; CHECK-NEXT:    sw $1, 12($fp)
-; CHECK-NEXT:    addiu $1, $zero, 1
-; CHECK-NEXT:    sw $1, 16($fp)
-; CHECK-NEXT:    addiu $1, $zero, 3
-; CHECK-NEXT:    sw $1, 8($fp)
-; CHECK-NEXT:    addiu $1, $zero, 4
-; CHECK-NEXT:    sw $1, 4($fp)
+; CHECK-NEXT:    balc OUTLINED_FUNCTION_6342aa443a2a9a5887d1350bbc1e09528fec5a00eb7c233d57781b9d3c73b1a4
 ; CHECK-NEXT:    lw $1, 16($fp)
 ; CHECK-NEXT:    bnez $1, $BB0_2
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  $BB0_4:
-; CHECK-NEXT:    addiu $1, $zero, 2
-; CHECK-NEXT:    sw $1, 12($fp)
-; CHECK-NEXT:    addiu $1, $zero, 1
-; CHECK-NEXT:    sw $1, 16($fp)
-; CHECK-NEXT:    addiu $1, $zero, 3
-; CHECK-NEXT:    sw $1, 8($fp)
-; CHECK-NEXT:    addiu $1, $zero, 4
-; CHECK-NEXT:    sw $1, 4($fp)
+; CHECK-NEXT:    balc OUTLINED_FUNCTION_6342aa443a2a9a5887d1350bbc1e09528fec5a00eb7c233d57781b9d3c73b1a4
 ; CHECK-NEXT:  $BB0_5:
-; CHECK-NEXT:    addiu $2, $zero, 0
-; CHECK-NEXT:    move $sp, $fp
-; CHECK-NEXT:    lw $fp, 24($sp) # 4-byte Folded Reload
-; CHECK-NEXT:    lw $ra, 28($sp) # 4-byte Folded Reload
-; CHECK-NEXT:    jr $ra
-; CHECK-NEXT:    addiu $sp, $sp, 32
+; CHECK-NEXT:    bc OUTLINED_FUNCTION_c71f1bd49b1f15e9cb47cb98c9592cfb18460320a4024fa283e78fa0f1fb5852
 ;
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0:
@@ -142,9 +122,25 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
 ; CHECK-NEXT:    sw $2, 16($fp)
 ; CHECK-NEXT:    sw $3, 8($fp)
 ; CHECK-NEXT:    sw $4, 4($fp)
+; CHECK-NEXT:    bc OUTLINED_FUNCTION_c71f1bd49b1f15e9cb47cb98c9592cfb18460320a4024fa283e78fa0f1fb5852
+;
+; CHECK-LABEL: OUTLINED_FUNCTION_6342aa443a2a9a5887d1350bbc1e09528fec5a00eb7c233d57781b9d3c73b1a4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addiu $1, $zero, 2
+; CHECK-NEXT:    sw $1, 12($fp)
+; CHECK-NEXT:    addiu $1, $zero, 1
+; CHECK-NEXT:    sw $1, 16($fp)
+; CHECK-NEXT:    addiu $1, $zero, 3
+; CHECK-NEXT:    sw $1, 8($fp)
+; CHECK-NEXT:    addiu $1, $zero, 4
+; CHECK-NEXT:    sw $1, 4($fp)
+; CHECK-NEXT:    jrc $ra
+;
+; CHECK-LABEL: OUTLINED_FUNCTION_c71f1bd49b1f15e9cb47cb98c9592cfb18460320a4024fa283e78fa0f1fb5852:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addiu $2, $zero, 0
 ; CHECK-NEXT:    move $sp, $fp
-; CHECK-NEXT:    lw $fp, 24($sp) # 4-byte Folded Reload
-; CHECK-NEXT:    lw $ra, 28($sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw $fp, 24($sp)
+; CHECK-NEXT:    lw $ra, 28($sp)
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    addiu $sp, $sp, 32

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/mips_generated_funcs.ll.nogenerated.expected

@@ -1,7 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -enable-machine-outliner -mtriple=mips-unknown-linux < %s | FileCheck %s
-;
-; NOTE: Machine outliner doesn't run.
 @x = global i32 0, align 4
 
 define dso_local i32 @check_boundaries() #0 {
@@ -29,33 +27,14 @@ define dso_local i32 @check_boundaries() #0 {
 ; CHECK-NEXT:    j $BB0_5
 ; CHECK-NEXT:    sw $1, 8($fp)
 ; CHECK-NEXT:  $BB0_3:
-; CHECK-NEXT:    addiu $1, $zero, 2
-; CHECK-NEXT:    sw $1, 12($fp)
-; CHECK-NEXT:    addiu $1, $zero, 1
-; CHECK-NEXT:    sw $1, 16($fp)
-; CHECK-NEXT:    addiu $1, $zero, 3
-; CHECK-NEXT:    sw $1, 8($fp)
-; CHECK-NEXT:    addiu $1, $zero, 4
-; CHECK-NEXT:    sw $1, 4($fp)
+; CHECK-NEXT:    balc OUTLINED_FUNCTION_6342aa443a2a9a5887d1350bbc1e09528fec5a00eb7c233d57781b9d3c73b1a4
 ; CHECK-NEXT:    lw $1, 16($fp)
 ; CHECK-NEXT:    bnez $1, $BB0_2
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  $BB0_4:
-; CHECK-NEXT:    addiu $1, $zero, 2
-; CHECK-NEXT:    sw $1, 12($fp)
-; CHECK-NEXT:    addiu $1, $zero, 1
-; CHECK-NEXT:    sw $1, 16($fp)
-; CHECK-NEXT:    addiu $1, $zero, 3
-; CHECK-NEXT:    sw $1, 8($fp)
-; CHECK-NEXT:    addiu $1, $zero, 4
-; CHECK-NEXT:    sw $1, 4($fp)
+; CHECK-NEXT:    balc OUTLINED_FUNCTION_6342aa443a2a9a5887d1350bbc1e09528fec5a00eb7c233d57781b9d3c73b1a4
 ; CHECK-NEXT:  $BB0_5:
-; CHECK-NEXT:    addiu $2, $zero, 0
-; CHECK-NEXT:    move $sp, $fp
-; CHECK-NEXT:    lw $fp, 24($sp) # 4-byte Folded Reload
-; CHECK-NEXT:    lw $ra, 28($sp) # 4-byte Folded Reload
-; CHECK-NEXT:    jr $ra
-; CHECK-NEXT:    addiu $sp, $sp, 32
+; CHECK-NEXT:    bc OUTLINED_FUNCTION_c71f1bd49b1f15e9cb47cb98c9592cfb18460320a4024fa283e78fa0f1fb5852
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
@@ -120,12 +99,7 @@ define dso_local i32 @main() #0 {
 ; CHECK-NEXT:    sw $2, 16($fp)
 ; CHECK-NEXT:    sw $3, 8($fp)
 ; CHECK-NEXT:    sw $4, 4($fp)
-; CHECK-NEXT:    addiu $2, $zero, 0
-; CHECK-NEXT:    move $sp, $fp
-; CHECK-NEXT:    lw $fp, 24($sp) # 4-byte Folded Reload
-; CHECK-NEXT:    lw $ra, 28($sp) # 4-byte Folded Reload
-; CHECK-NEXT:    jr $ra
-; CHECK-NEXT:    addiu $sp, $sp, 32
+; CHECK-NEXT:    bc OUTLINED_FUNCTION_c71f1bd49b1f15e9cb47cb98c9592cfb18460320a4024fa283e78fa0f1fb5852
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4

llvm/utils/lit/lit/llvm/config.py

@@ -122,6 +122,8 @@ def __init__(self, lit_config, config):
             elif re.match(r'^arm.*', target_triple):
                 features.add('target-arm')
 
+        features.add('nanomips')
+
         use_gmalloc = lit_config.params.get('use_gmalloc', None)
         if lit.util.pythonize_bool(use_gmalloc):
             # Allow use of an explicit path for gmalloc library.