Liberty view for IO cells update. #104
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…n make it feasible to run ORFS flow Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
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See all following cells have the same issue.
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Can you move both IO cells at the beginning or move Vss/Vdd cells from the beginning here?
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I don't see any obvious issue here with these two timings. I wonder if timings are missing in the pin c2p and pin c2p_en definitions...
…EF. Dummy modules and cells added in Verilog and Liberty files Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
…ters added Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
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There were some updates, which limit the cells to the list defined in Also some properties of the filler cell were added together with a fix on positive/negative unate. I ran ORFS using these updated views and still got some issues that are listed below: Maybe @stafverhaegen-chipflow could provide some solutions for |
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I can change version to 5.7 if that is confirmed to solve the problem. |
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Could it be missing pin definitions for power/ground? All IOPad cells have following pg_pins but not Corner/Filler cells. |
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@FatsieFS feel free to provide downgraded version of the LEF. As for |
…v_pmos Signed-off-by: KrzysztofHerman <herman@ihp-microelectronics.com>
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@KrzysztofHerman |
The updated view contains definition of all IO cells provided in the library hence it is feasible to use it in ORFS to design a pad ring.