Brendan Lynskey · Portfolio home · Interactive sites
The families of AI silicon, compared on the same work: GPUs, systolic designs, wafer-scale engines, compiler-scheduled SRAM chips, reconfigurable dataflow, meshes of small cores, FPGAs and edge NPUs, and in-memory compute. For each: where the weights live, what moves on each step, and who decides when it moves.
Live index: https://brendanjameslynskey.github.io/LLM_Hub_AI_Accelerators/
The three decks are the slide companion to AI Accelerators Explained, ten animated chapters in the Hardware track (beside GPU Kernels, Systolic Arrays and AI Racks Explained). Every number in the decks is computed by the site's tested model, with every specification sourced and dated in its results.md.
| # | Title | Status | Description | Site chapters |
|---|---|---|---|---|
| 01 | The Design Space and the Memory Wall | live | The three axes and the eight families; the running workload (a Llama decoder); GPUs and systolic designs as the baseline; capacity as the first trade; every family side by side; bounds against published figures; what the families are converging on. | 1, 2, 3, 10 |
| 02 | SRAM Machines: Wafers, LPUs and IPUs | live | Why SRAM; a wafer of 84 dies and how defects are survived; models split across wafers and weight streaming; the GroqChip's static schedule and a 576-chip chain; what the published speeds say about the bound; the IPU's bulk-synchronous tiles. | 4, 5, 6 |
| 03 | Dataflow, Meshes, Edge and In-Memory | live | A layer kernel by kernel vs fused; three tiers of memory and the SN40L paper's measured speed; a mesh of cores split over cards; a batch-1 decode at narrower weights on an NPU or FPGA; a decoder on phase-change crossbars, and what it costs in capacity and precision. | 6, 7, 8, 9 |
- NVIDIA GPU Architectures and Google TPUs: the two baseline families in depth.
- GPU Kernels Explained, Systolic Arrays Explained and AI Racks Explained: inside one GPU, inside one matrix engine, and the racks these chips go into.
- Fourier Optics for Inference and Compute in Transit: computing with light, the analogue route these decks mention but do not cover.
Part of the LLMs hub — an index of presentation series for AI/LLM engineers.