Welcome to the HDL Projects repository! This central repository contains HDL designs, examples, and comprehensive documentation for working with Field Programmable Gate Arrays (FPGAs), ASICs chips and Complex Programmable Logic Devices (CPLDs).
- Gowin Tang Nano (1K & 20K)
- Altera MAX II
cores/: Reusable hardware blocks (IPs) that are platform-agnostic (e.g., clock dividers, UART controllers);systems/: Complete embedded projects (Top-levels) targeted for specific FPGA boards (e.g., Altera MAX II, Tang Nano);docs/: Comprehensive guides, installation tutorials, and workflow steps. Start here if you are setting up your environment;scripts/: Automation scripts (e.g., environment setup).
The educational processor implementations have been moved to their own dedicated repositories:
Choose the guide that matches your OS and target FPGA:
- Tang Nano (Open Source / Linux):
docs/suit_install.md - Quartus Prime Lite (Windows/Linux):
docs/quartus_install.md
Once installed, follow these guides to run your first project:
- Tang Nano:
docs/tangnano_workflow.md(Gowin IDE and Open-source Toolchain) - Altera MAX II:
docs/altera_workflow.md(Quartus Prime Lite)
This repository is dual-licensed:
- Open Source (GPLv3): The hardware IPs (cores) and systems in this repository are available for free under the GNU General Public License v3.0. This means you can use, modify, and distribute them freely for educational, personal, or open-source projects, provided that your derived work is also open-sourced under the GPLv3.
- Commercial License: If you intend to use these IPs in a closed-source proprietary commercial product and do not wish to release your product's source code under the GPLv3, you must obtain a commercial license. Please contact the author for commercial licensing options.