MIPS Processor Implementation

This repository contains Hardware Description Language (HDL) implementations of the MIPS (Microprocessor without Interlocked Pipeline Stages) instruction set architecture.

Overview

The MIPS architecture is a classic Reduced Instruction Set Computer (RISC) design, widely used in academic environments and embedded hardware. This project aims to provide synthesizable cores for FPGA usage.

Project Structure Index

The project is structured as follows, containing components, testbenches, and waveforms for simulation:

mips32/
├── components/
│   ├── MIPS.v                 # Top-level MIPS module
│   ├── datapath.v             # Datapath structure
│   ├── alu_unit.v             # Arithmetic Logic Unit (ALU)
│   ├── alu_control.v          # ALU Control Unit
│   ├── control_unit.v         # Main Control Unit
│   ├── data_memory.v          # RAM Data Memory
│   ├── instruction_fetch.v    # Instruction Fetch module
│   ├── instruction_memory.v   # ROM Instruction Memory
│   ├── program_counter.v      # Program Counter (PC)
│   ├── register_files.v       # Register File (32x32 bits)
│   └── sign_extension.v       # 16-to-32 bit Sign Extender
├── testbenches/
│   ├── instruction_R_tb.v         # Testbench for R-Type instructions
│   ├── instruction_R_I_tb.v       # Testbench for R-Type and I-Type instructions
│   ├── instruction_J_tb.v         # Testbench for J-Type instructions
│   └── instruction_fibonacci_tb.v # Integration testbench using Fibonacci sequence
└── waveforms/
    ├── fibonacci.vcd          # Waveform output for Fibonacci test
    └── fibonacci_mips.vcd     # Waveform output for Fibonacci MIPS test

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32-Bit Architecture (mips32)

Instruction Format

The 32-bit MIPS instructions have a fixed size of 32 bits and follow predefined formats to facilitate decoding in the single-cycle datapath.

Instruction Types

• R-Type (Register): Arithmetic and logical instructions that operate exclusively with registers.
• I-Type (Immediate): Data transfer instructions (memory) and conditional branches using a 16-bit immediate value.
• J-Type (Jump): Unconditional jump instructions.

Operations

The processor supports the following basic operations:

• Arithmetic and Logical: add, sub, and, or, slt
• Data Transfer: lw (load word), sw (store word)
• Branches: beq (branch on equal), j (jump)

Implementation Files

The single-cycle datapath is modularized into several Verilog files located in the mips32/components/ directory:

• program_counter.v: Program Counter (PC).
• instruction_fetch.v / instruction_memory.v: Instruction Fetch and ROM memory.
• data_memory.v: RAM Data memory.
• register_files.v: Register file (32x32 bits).
• alu_unit.v: Arithmetic Logic Unit (ALU).
• sign_extension.v: 16-to-32 bit sign extender.
• control_unit.v and alu_control.v: Main control and ALU control units.
• datapath.v and MIPS.v: Top-level modules structuring the datapath.

Testing

Testbenches validate the functionality of isolated instructions as well as their joint operation. They are located in the mips32/testbenches/ directory (note: directory is currently named testebenches in the file system):

• Individual tests for R and I formats (add, sub, lw, sw).
• Conditional and unconditional branch tests (beq, j).
• Integration test using the Fibonacci sequence in Assembly.

Waveform Output

The results from testbench simulations are exported to waveform files with a .vcd extension (located in mips32/waveforms/), which can be visually analyzed using software like GTKWave.