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[Meta Schedule][M3c] Schedule Rules, Mutator & Postprocs (apache#485) [Meta Schedule][M3c] PostOrderApply (apache#486) Fix Post Order Apply (apache#490) [MetaSchedule] Relay Integration (apache#489) [M3c][Meta Schedule] Add Trace Correctness Test for PostOrderApply (apache#492) Fix replay trace. (apache#493) [M3c][Meta Schedule] Implement the Replay Func class. (apache#495) [PR] Test script for meta-schedule task extraction. Interface to load… (apache#494) [Meta Schedule Refactor] Get child blocks (apache#500) Read-at && Write-at (apache#497) [M3c][Meta Schedule] Measure Callbacks (apache#498) [Bug] Fix Infinite Loop Caused When Calling Methods Not Overrided In PyClass (apache#496) [MetaSchedule] Sample-Perfect-Tile (apache#501) [MetaSchedule] TE Workloads (apache#502) [TensorIR] GetProducer, GetConsumer (apache#506) [MetaScheduleRefactor] Annotate&Unannotate (apache#505) [MetaSchedule] Multi-Level-Tiling & Auto-Inline (apache#503) [Tests] Add unittests for auto-inline and multi-level-tiling (apache#508) [Meta Schedule] Minor Fixes (apache#507) [MetaSchedule] Rewrite Cooperative-Fetching / Unbound-Block / Reduction-Block (apache#509) [MetaSchedule] Rewrite Parallel-Vectorize-Unroll / Verify-GPU / Disallow-Dynamic-Loops (apache#499) [Meta Schedule] Add Helper Function & Minor Modification (apache#512) [MetaSchedule] Test for Rewrite Parallel-Vectorize-Unroll (apache#513) [Meta Schedule] Feature Extractor & Cost Model (apache#510) Blockize & Tensorize (apache#514) Layout Rewriting: Suggest-Index-Map (apache#520) [MetaSchedule] Parallel-Vectorize-Unroll & Random-Compute-Location (apache#516) [Meta Schedule] Per-Store-Feature (apache#521) Add traced schedule for blockize & tensorize (apache#526) [Meta Schedule] Add XGBoost Model & Random Model (apache#519) User-Interface: Tune-TIR (apache#525) User-Interface: Tune-TE (apache#527) [Minor] More logging on python (apache#528) Get CUDA tuning working (apache#529) [MetaSchedule] TensorRT BYOC (apache#518) [BugFix] LocalBuilder API (apache#531) [Meta Schedule] Add Cost Model Update Measure Callback (apache#530) [Bugfix] BuilderInput with default params (apache#532) [MetaSchedule] Mutator-Tile-Size, Mutate-Parallel, Mutate-Unroll (apache#534) [Meta Schedule] Evolutionary Search (apache#522) [BugFix] Remove duplicated definition of MakeMultinomialSampler (apache#535) [Meta Schedule] Fix some bugs (apache#537) Initiate Experiments for CPU Performance Alignment with Ansor (apache#538) [Meta Schedule] Tweak experiment scripts (apache#539) [Meta Schedule] Initiate experiments on CUDA (apache#540) [TIR][Schedule] Buffer transform (apache#523) Auto Tensor Core (apache#524) Working on Evo Search (apache#542) [Meta Schedule] Add Replay Tuning Interface (apache#543) Evolutionary Search on CPU (apache#544) Misc improvement over the error message (apache#545) [TIR][Schedule] Software pipelining (apache#533) [Meta Schedule Refactor] fixing unit tests (apache#547) [MetaSchedule] Mutator-Compute-Location (apache#548) Misc Improvement of Evolutionary Search (apache#549) Hotfix for software pipeline (apache#552) Misc Improvement (apache#550) [Cherry-Pick][TensorIR] Primitive "SetScope" (apache#9738) (apache#555) Rule RFactor (apache#551) [MemHammer] Rewrite Rules (apache#554) [MetaSchedule] Schedule Rule: Cross-Thread Reduction (apache#556) [MetaSchedule] Performance Alignment - NRM and SFM (CUDA) (apache#559) [MetaSchedule] Perf Alignment - NRM on CUDA (apache#560) [TIR] Reorder the block iters of the blocks generated by RFactor (apache#561) Removing 2 unit tests for software pipelining (apache#562) [MemHammer] Lower Pass + Unittests (apache#557) Perf Align: Remove Auto-inline before Multi-level-tiling (apache#564) Fix Sketch Generation Unittests (apache#565) speed up VerifyGpuCode (apache#568) [Performance Align] fixing codegen problems (apache#569) [Meta schedule] improve search space (apache#1) Hot fix for bound predicate (apache#3) [Meta Schedule] Update Tune Relay (apache#4) [Performance Align] fixing codegen problems (apache#5) [PerfAlign] NRM & SFM on Raspi Aligned (apache#6) [BugFix] Apply bound predicate directly to loops when possible (apache#12) [BugFix] Fix CrossThreadReduction on CUDA (apache#13) [MetaSchedule] Enable BertTuning with MetaScheduler (apache#11) [Minor][MemHammer] Minor tweaks in code review (apache#14) [Meta Schedule] Add customizable search space to PostOrderApply. (apache#16) Fix cooperative fetching (apache#17) Fixes for codegen (apache#18) [Hotfix] A unittest (apache#19) Fix for GRP sketch gen (apache#21) Add threadIdx filtering in Multi-Level-Tiling and Verify-GPU-Code (apache#20) [BugFix][TIR] Fix cross-thread reduction when single reduction loop with predicate (apache#10016) (apache#22) [MemHammer][Refactor] Code Review (apache#15) [Meta Schedule] Add Winograd Test for Customizable Search Space (apache#24) Import & Cache Mechanism (apache#26) [BugFix] Fix Winograd Test Script (apache#25) Add task extraction & caching (apache#27) A few fixes for task extraction (apache#28) Co-authored-by: Siyuan Feng <Hzfengsy@sjtu.edu.cn> Co-authored-by: Bohan Hou <32121147+spectrometerHBH@users.noreply.github.com> Co-authored-by: Hongyi Jin <3231950289@qq.com> Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com> Co-authored-by: Junru Shao <junrushao1994@gmail.com> Co-authored-by: Wuwei Lin <wuwei@apache.org> Co-authored-by: Sunghyun Park <49998730+sunggg@users.noreply.github.com> Co-authored-by: Xiyou Zhou <xiyou@octoml.ai>
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.github/CODEOWNERS

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# Licensed to the Apache Software Foundation (ASF) under one
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# or more contributor license agreements. See the NOTICE file
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# distributed with this work for additional information
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# regarding copyright ownership. The ASF licenses this file
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# to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance
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# with the License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing,
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# software distributed under the License is distributed on an
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# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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# KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations
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# under the License.
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# Github code owners file
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# This file is used as a convenient tool to map
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# committers' areas of expertise and faciliate the review process.
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#
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# This may not be the non-comprehensive list and is meant to be
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# updated over time.
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# Per ASF policy, committer have global write permission.
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# We normally recommend committers to shepherd code in their area of expertise.
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* @apache/tvm-committers
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# Order is important; the last matching pattern takes the most precedence.
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# The sub modules should be ordered first by depth.
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# Making sure we append new sub-module rules after exisiting modules rules.
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##############################
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# Top-level Fallbacks
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##############################
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include/** @tqchen @jroesch @yzhliu @icemelon @junrushao1994 @comaniac @zhiics
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src/** @tqchen @jroesch @yzhliu @icemelon @junrushao1994 @comaniac @zhiics
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apps/** @tqchen @jroesch @yzhliu @icemelon @junrushao1994 @comaniac @zhiics
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python/** @tqchen @jroesch @yzhliu @icemelon @junrushao1994 @comaniac @zhiics
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# Thirdparty license audit
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3rdparty/** @tqchen @jroesch
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licenses/** @tqchen @jroesch
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# JVM language
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jvm/** @yzhliu
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# Golang
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golang/** @srkreddy1238
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# WASM
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web/** @tqchen @jroesch
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# Docker
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docker/** @areusch @leandron @jroesch
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# Conda
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conda/** @tqchen @junrushao1994 @comaniac
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# CMake
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cmake/** @jroesch @tqchen @areusch @junrushao1994 @comaniac
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# rust bindings
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rust/** @jroesch @nhynes @nhynes
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# vta
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vta/** @tmoreau89 @vegaluisjose
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# docs
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docs/** @comaniac @junrushao1994 @tqchen @jroesch @areusch @yzhliu @merrymercy @icemelon
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tutorials/** @comaniac @junrushao1994 @tqchen @jroesch @areusch @yzhliu @merrymercy @icemelon
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# tests
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tests/** @comaniac @junrushao1994 @tqchen @jroesch @areusch @yzhliu @merrymercy @icemelon
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##############################
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# Specific modules
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##############################
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# automation related
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src/auto_scheduler/** @merrymercy @jcf94 @comaniac @junrushao1994 @vinx13 @Hzfengsy
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include/tvm/auto_scheduler/** @merrymercy @jcf94 @comaniac @junrushao1994 @vinx13 @Hzfengsy
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python/tvm/auto_scheduler/** @merrymercy @jcf94 @comaniac @junrushao1994 @vinx13 @Hzfengsy
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python/tvm/autotvm/** @merrymercy @jcf94 @comaniac @junrushao1994 @vinx13
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# node system and reflection
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src/node/** @junrushao1994 @vinx13 @tqchen @jroesch @comaniac
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include/tvm/node/** @junrushao1994 @vinx13 @tqchen @jroesch @comaniac
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# ir: Common IR
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src/ir/** @junrushao1994 @vinx13 @tqchen @jroesch @comaniac
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include/tvm/ir/** @junrushao1994 @vinx13 @tqchen @jroesch @comaniac
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python/tvm/ir/** @junrushao1994 @vinx13 @tqchen @jroesch @comaniac
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# tir
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src/tir/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi @were @Hzfengsy
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include/tvm/tir/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi @were @Hzfengsy
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python/tvm/tir/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi @were @Hzfengsy
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# te
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src/te/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi @were
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include/tvm/te/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi @were
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python/tvm/te/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi @were
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# target
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src/target/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi
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include/tvm/target/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi
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python/tvm/target/** @junrushao1994 @vinx13 @tqchen @kparzysz-quic @ZihengJiang @masahi
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# arith: Arithmetic module and simplifiers
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src/arith/** @tqchen @junrushao1994 @vinx13
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include/tvm/arith/** @tqchen @junrushao1994 @vinx13
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python/tvm/arith/** @tqchen @junrushao1994 @vinx13
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# parser
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src/parser/** @jroesch @slyubomirsky
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# runtime
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src/runtime/** @vinx13 @tqchen @FronzenGene @liangfu @areusch @tmoreau89 @ajtulloch @masahi @kazum @ZihengJiang @junrushao1994
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include/tvm/runtime/** @vinx13 @tqchen @FronzenGene @liangfu @areusch @tmoreau89 @ajtulloch @masahi @kazum @ZihengJiang @junrushao1994
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python/tvm/runtime/** @vinx13 @tqchen @FronzenGene @liangfu @areusch @tmoreau89 @ajtulloch @masahi @kazum @ZihengJiang @junrushao1994
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# runtime/micro
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src/runtime/micro/** @areusch @liangfu @tmoreau89 @manupa-arm
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src/runtime/crt/** @areusch @liangfu @tmoreau89 @manupa-arm
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include/tvm/runtime/crt/** @areusch @liangfu @tmoreau89 @manupa-arm
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include/tvm/runtime/micro/** @areusch @liangfu @tmoreau89 @manupa-arm
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python/tvm/micro/** @areusch @liangfu @tmoreau89 @manupa-arm
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# relay
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src/relay/** @jroesch @slyubomirsky @icemelon @MarisaKirisame @ZihengJiang @yzhliu @vinx13 @mbrookhart @jwfromm @zhiics @anijain2305 @wweic @eqy @junrushao1994
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include/tvm/relay/** @jroesch @slyubomirsky @icemelon @MarisaKirisame @ZihengJiang @yzhliu @vinx13 @mbrookhart @jwfromm @zhiics @anijain2305 @wweic @eqy @junrushao1994
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python/tvm/relay/** @jroesch @slyubomirsky @icemelon @MarisaKirisame @ZihengJiang @yzhliu @vinx13 @mbrookhart @jwfromm @zhiics @anijain2305 @wweic @eqy @junrushao1994
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# relay/qnn
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src/relay/qnn/** @jwfromm @anijain2305 @ZihengJiang
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inlcude/tvm/relay/qnn/** @jwfromm @anijain2305 @ZihengJiang
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python/tvm/relay/qnn/** @jwfromm @anijain2305 @ZihengJiang
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# relay/backend/contrib: BYOC
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src/relay/backend/contrib/** @zhiics @trevor-m @comaniac @mbaret @manupa-arm
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# relay/frontends
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python/tvm/relay/frontend/** @jwfromm @mbrookhart @srkreddy1238 @siju-samuel @Huyuwei @hlu1 @kazum @PariksheetPinjari909
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# topi: Operator definitions
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src/topi/** @Laurawly @Huyuwei @kevinthesun @jwfromm @vinx13 @masahi @FronzenGene @yzhliu @mbrookhart @ZihengJiang @jcf94
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include/tvm/topi/** @Laurawly @Huyuwei @kevinthesun @jwfromm @vinx13 @masahi @FronzenGene @yzhliu @mbrookhart @ZihengJiang @jcf94
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python/tvm/topi/** @Laurawly @Huyuwei @kevinthesun @jwfromm @vinx13 @masahi @FronzenGene @yzhliu @mbrookhart @ZihengJiang @jcf94
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# tvm/driver/
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python/tvm/driver/** @leandron @jwfromm @tqchen @jroesch
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# tvm/driver/tvmc
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python/tvm/driver/tvmc/** @leandron @jwfromm

include/tvm/arith/int_set.h

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@@ -169,6 +169,14 @@ Map<Var, IntSet> ConvertDomMap(const std::unordered_map<const VarNode*, IntSet>&
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* \return An integer set that can cover all the possible values of e.
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*/
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IntSet EvalSet(PrimExpr e, const Map<IterVar, IntSet>& dom_map);
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/*!
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* \brief Same as EvalSet, but takes Map<Var, IntSet>
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*
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* \param e The expression to be evaluated.
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* \param dom_map The domain of each variable.
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* \return An integer set that can cover all the possible values of e.
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*/
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IntSet EvalSet(PrimExpr e, const Map<Var, IntSet>& dom_map);
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/*!
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* \brief Same as EvalSet, but takes unordered_map
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*
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* \return An integer set that can cover all the possible values of e.
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*/
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IntSet EvalSet(PrimExpr e, const std::unordered_map<const tir::VarNode*, IntSet>& dom_map);
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/*!
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* \brief Same as EvalSet, but takes Array<PrimExpr>
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*
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* \param exprs The expressions to be evaluated.
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* \param dom_map The domain of each variable.
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* \return An array of integer sets that can cover all the possible values.
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*/
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Array<IntSet> EvalSet(const Array<PrimExpr>& exprs, const Map<Var, IntSet>& dom_map);
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/*!
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* \brief Find an symbolic integer set that contains is union over
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* all the possible conditional values in dom_map.

include/tvm/meta_schedule/builder.h

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@@ -32,7 +32,7 @@ class BuilderInputNode : public runtime::Object {
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IRModule mod;
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/*! \brief The target to be built for. */
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Target target;
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/*! \brief The optional parameters used for build */
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/*! \brief Parameters for Relay build module. */
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Optional<Map<String, runtime::NDArray>> params;
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void VisitAttrs(tvm::AttrVisitor* v) {
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* \brief Constructor of BuilderInput.
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* \param mod The IRModule to be built.
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* \param target The target to be built for.
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* \param params The optional parameters used for build
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* \param params Parameters for Relay build module.
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*/
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TVM_DLL explicit BuilderInput(IRModule mod, Target target,
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Optional<Map<String, runtime::NDArray>> params = NullOpt);

include/tvm/meta_schedule/schedule_rule.h

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* \param tile_binds For each level of tiles, which thread axis it is bound to. Recommended:
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* - NullOpt on CPU
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* - [blockIdx.x, vthread.x, threadIdx.x] on GPU
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* \param use_tensor_core Whether to apply tensor core wmma intrinsic for the computation
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* \param max_innermost_factor The maximum size of the innermost factor. NullOpt means no limit
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* NullOpt means disable vectorization
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*/
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TVM_DLL static ScheduleRule MultiLevelTiling(String structure, //
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Optional<Array<String>> tile_binds, //
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bool use_tensor_core, //
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Optional<Integer> max_innermost_factor, //
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Optional<Array<Integer>> vector_load_lens, //
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Optional<Map<String, ObjectRef>> reuse_read, //

include/tvm/meta_schedule/tune_context.h

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v->Visit("rand_state", &rand_state);
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v->Visit("num_threads", &num_threads);
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v->Visit("is_stopped", &is_stopped);
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v->Visit("builder_results", &builder_results);
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v->Visit("runner_futures", &runner_futures);
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v->Visit("measure_candidates", &measure_candidates);
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}
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include/tvm/tir/function.h

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TVM_DEFINE_OBJECT_REF_COW_METHOD(LinkedParamNode);
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};
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/*! \brief A mapping from multi-dimensional indices to another set of multi-dimensional indices */
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class IndexMapNode : public Object {
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public:
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/*! \brief The source indices */
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Array<Var> src_iters;
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/*! \brief The target indices */
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Array<PrimExpr> tgt_iters;
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void VisitAttrs(tvm::AttrVisitor* v) {
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v->Visit("src_iters", &src_iters);
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v->Visit("tgt_iters", &tgt_iters);
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}
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/*!
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* \brief Take `inputs` as the source indices and return the corresponding target indices.
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* \param inputs The source indices.
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* \return The target indices.
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*/
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Array<PrimExpr> Apply(const Array<PrimExpr>& inputs) const;
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/*!
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* \brief Map a shape to the output space
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* \param shape The shape in the source space
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* \return The shape in the target space
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*/
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Array<PrimExpr> MapShape(const Array<PrimExpr>& shape) const;
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/*!
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* \brief Convert to string representation in Python.
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* \return The stringified lambda expression in Python.
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*/
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String ToPythonString() const;
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static constexpr const char* _type_key = "tir.IndexMap";
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TVM_DECLARE_FINAL_OBJECT_INFO(IndexMapNode, Object);
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};
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/*!
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* \brief Managed reference to IndexMapNode.
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* \sa IndexMapNode
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*/
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class IndexMap : public ObjectRef {
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public:
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/*!
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* \brief Constructor.
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* \param src_iters The source indices.
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* \param tgt_iters The target indices.
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*/
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explicit IndexMap(Array<Var> src_iters, Array<PrimExpr> tgt_iters);
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/*!
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* \brief Create an index map from a packed function
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* \param ndim The number of dimensions
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* \param func The function to be applied
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* \return The created index map
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*/
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static IndexMap FromFunc(int ndim, runtime::TypedPackedFunc<Array<PrimExpr>(Array<Var>)> func);
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TVM_DEFINE_OBJECT_REF_METHODS(IndexMap, ObjectRef, IndexMapNode);
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};
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/*!
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include/tvm/tir/schedule/schedule.h

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*/
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virtual BlockRV CacheWrite(const BlockRV& block_rv, int write_buffer_index,
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const String& storage_scope) = 0;
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/******** Schedule: Data movement ********/
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virtual BlockRV ReadAt(const LoopRV& loop_rv, const BlockRV& block_rv, int read_buffer_index,
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const String& storage_scope) = 0;
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virtual BlockRV WriteAt(const LoopRV& loop_rv, const BlockRV& block_rv, int write_buffer_index,
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const String& storage_scope) = 0;
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/******** Schedule: Compute location ********/
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/*!
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virtual void Unannotate(const BlockRV& block_rv, const String& ann_key) = 0;
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/******** Schedule: Layout transformation ********/
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/*!
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* \brief Apply a transformation represented by IndexMap to buffer
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* \details The indices and the access region to the target buffer is transformed by the given
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* index_map. The index_map is used to infer the new shape of the buffer. Buffer must be either
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* a function parameter, or allocated in a block (it cannot be a buffer subregion created via
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* 'match_buffer').
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* \param block_rv The block that accesses the target buffer.
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* \param buffer_index The index of the buffer in block's read or write region.
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* \param is_write_index Whether the buffer_index is the index of the block's write region.
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* \param index_map The transformation to apply.
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*/
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virtual void TransformLayout(const BlockRV& block_rv, int buffer_index, bool is_write_index,
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const IndexMap& index_map) = 0;
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/******** Schedule: Misc ********/
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/*! \brief A no-op that marks the start of postprocessing phase of scheduling */
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virtual void EnterPostproc() = 0;

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