An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …

Neural Network accelerator powered by MVUs and RISC-V.

A FPGA friendly 32 bit RISC-V CPU implementation

Integration of two camera modules to Basys 3 FPGA

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

A Barrel design of RV32I

The Ultra-Low Power RISC-V Core

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Individual Contributions to my team's CPEN 391 final project. I developed the video frame capture system for the D8M, created Avalon slaves for hardware-software interfacing and the DCT hardware ac…

A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard

Hardware accelerator for convolutional neural networks

果壳处理器研究小组(Topic:基于RISCV64果核处理器的卷积神经网络加速器研究)

除法器

FPGA project

Verilog Generator of Neural Net Digit Detector for FPGA

⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform

Real time face detection based on Arm Cortex-M3 DesignStart and FPGA

IC design and development should be faster，simpler and more reliable

基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现

Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The SoC worked not bad in the end the success rate up to 90%。.

A very simple and easy to understand RISC-V core.

七路图像在FPGA中实现拼接，代码会不断添加进来。

Hardware acceleration combines the flexibility of general-purpose processors, such as CPUs, with the efficiency of fully customized hardware, such as GPUs and ASICs, increasing efficiency by orders…

Convolutional accelerator kernel, target ASIC & FPGA

[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2