Merge git://git.denx.de/u-boot-fsl-qoriq

arch/arm/Kconfig

@@ -786,6 +786,20 @@ config TARGET_LS2080ARDB
 	  development platform that supports the QorIQ LS2080A
 	  Layerscape Architecture processor.
 
+config TARGET_LS2081ARDB
+	bool "Support ls2081ardb"
+	select ARCH_LS2080A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select ARCH_MISC_INIT
+	help
+	  Support for Freescale LS2081ARDB platform.
+	  The LS2081A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS2081A/LS2041A
+	  Layerscape Architecture processor.
+
 config TARGET_HIKEY
 	bool "Support HiKey 96boards Consumer Edition Platform"
 	select ARM64

arch/arm/cpu/armv8/Kconfig

@@ -91,6 +91,7 @@ config PSCI_RESET
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
+		   !TARGET_LS2081ARDB && \
 		   !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
 	help
 	  Most armv8 systems have PSCI support enabled in EL3, either through

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -163,11 +163,12 @@ endchoice
 config SYS_LS_PPA_FW_ADDR
 	hex "Address of PPA firmware loading from"
 	depends on FSL_LS_PPA
-	default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
-	default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
-	default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
-	default 0x500000 if SYS_LS_PPA_FW_IN_MMC
-	default 0x500000 if SYS_LS_PPA_FW_IN_NAND
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
+	default 0x400000 if SYS_LS_PPA_FW_IN_NAND
 
 	help
 	  If the PPA firmware locate at XIP flash, such as NOR or

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -98,7 +99,8 @@ static void fix_pcie_mmu_map(void)
 
 	/* Fix PCIE base and size for LS2088A */
 	if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
-	    (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
+	    (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
+	    (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 			switch (final_map[i].phys) {
 			case CONFIG_SYS_PCIE1_PHYS_ADDR:

arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

@@ -5,6 +5,7 @@ SoC overview
 	3. LS1012A
 	4. LS1046A
 	5. LS2088A
+	6. LS2081A
 
 LS1043A
 ---------
@@ -227,3 +228,13 @@ LS2088A SoC has 3 more similar SoC personalities
 
 3)LS2044A, few difference w.r.t. LS2084A:
        a) Four 64-bit ARM v8 Cortex-A72 CPUs
+
+LS2081A
+--------
+LS2081A is 40-pin derivative of LS2084A.
+So feature-wise it is same as LS2084A.
+Refer to LS2084A(LS2088A) section above for details.
+
+It has one more similar SoC personality
+1)LS2041A, few difference w.r.t. LS2081A:
+       a) Four 64-bit ARM v8 Cortex-A72 CPUs

arch/arm/dts/Makefile

@@ -175,7 +175,9 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
 	ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
 	ls1021a-iot-duart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
-	fsl-ls2080a-rdb.dtb
+	fsl-ls2080a-rdb.dtb \
+	fsl-ls2081a-rdb.dtb \
+	fsl-ls2088a-rdb-qspi.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \

arch/arm/dts/fsl-ls2081a-rdb.dts

@@ -0,0 +1,59 @@
+/*
+ * NXP LS2081A RDB board device tree source for QSPI-boot
+ *
+ * Author: Priyanka Jain <priyanka.jain@nxp.com>
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2081a RDB Board";
+	compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
+
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi;
+	};
+};
+
+&dspi {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q512a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: n25q512a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+	};
+
+	qflash1: n25q512a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <1>;
+	};
+};

arch/arm/dts/fsl-ls2088a-rdb-qspi.dts

@@ -0,0 +1,59 @@
+/*
+ * NXP ls2080a RDB board device tree source for QSPI-boot
+ *
+ * Author: Priyanka Jain <priyanka.jain@nxp.com>
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2080a RDB Board";
+	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
+
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi;
+	};
+};
+
+&dspi {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q512a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fs512s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+	};
+
+	qflash1: s25fs512s@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <1>;
+	};
+};

arch/arm/include/asm/arch-fsl-layerscape/cpu.h

@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015, Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -15,6 +16,8 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
 	CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
 	CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+	CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+	CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
 	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

@@ -1,6 +1,7 @@
 /*
  * LayerScape Internal Memory Map
  *
+ * Copyright (C) 2017 NXP Semiconductors
  * Copyright 2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -45,6 +46,9 @@
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
+#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01330000)
+#define GPIO4_GPDIR_ADDR			(GPIO4_BASE_ADDR + 0x0)
+#define GPIO4_GPDAT_ADDR			(GPIO4_BASE_ADDR + 0x8)
 
 #define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)

arch/arm/include/asm/arch-fsl-layerscape/soc.h

@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -54,6 +55,8 @@ struct cpu_type {
 #define SVR_LS2084A		0x870910
 #define SVR_LS2048A		0x870920
 #define SVR_LS2044A		0x870930
+#define SVR_LS2081A		0x870919
+#define SVR_LS2041A		0x870915
 
 #define SVR_DEV_LS2080A		0x8701
 

board/freescale/ls1043ardb/Makefile

@@ -7,6 +7,6 @@
 obj-y += ddr.o
 obj-y += ls1043ardb.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-$(CONFIG_NET) += eth.o
 obj-y += cpld.o
 endif

board/freescale/ls1046ardb/Makefile

@@ -7,6 +7,6 @@
 obj-y += ddr.o
 obj-y += ls1046ardb.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-$(CONFIG_NET) += eth.o
 obj-y += cpld.o
 endif

board/freescale/ls1046ardb/README

@@ -59,14 +59,14 @@ Start Address	 End Address	 Description		Size
 QSPI flash map:
 Start Address    End Address     Description		Size
 0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI		1MB
-0x00_4010_0000 - 0x00_401F_FFFF  U-Boot 		1MB
-0x00_4020_0000 - 0x00_402F_FFFF  U-Boot Env		1MB
-0x00_4030_0000 - 0x00_403F_FFFF  FMan ucode		1MB
-0x00_4040_0000 - 0x00_404F_FFFF  UEFI			1MB
-0x00_4050_0000 - 0x00_406F_FFFF  PPA			2MB
-0x00_4070_0000 - 0x00_408F_FFFF  Secure boot header
-			         + bootscript		2MB
-0x00_4090_0000 - 0x00_40FF_FFFF  Reserved		7MB
+0x00_4010_0000 - 0x00_402F_FFFF  U-Boot 		2MB
+0x00_4030_0000 - 0x00_403F_FFFF  U-Boot Env		1MB
+0x00_4040_0000 - 0x00_405F_FFFF  PPA			2MB
+0x00_4060_0000 - 0x00_408F_FFFF  Secure boot header
+				 + bootscript		3MB
+0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
+0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
+0x00_4098_0000 - 0x00_40FF_FFFF  Reserved		6MB
 0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
 
 Booting Options

board/freescale/ls2080aqds/README

@@ -89,6 +89,19 @@ c) NAND boot
 d) SD boot
 e) QSPI boot
 
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Secure Headers			0x00600000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
 Environment Variables
 ---------------------
 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined

board/freescale/ls2080ardb/Kconfig

@@ -16,3 +16,21 @@ config SYS_CONFIG_NAME
 source "board/freescale/common/Kconfig"
 
 endif
+
+if TARGET_LS2081ARDB
+
+config SYS_BOARD
+	default "ls2080ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls2080ardb"
+
+source "board/freescale/common/Kconfig"
+
+endif

board/freescale/ls2080ardb/MAINTAINERS

@@ -7,6 +7,16 @@ F:	include/configs/ls2080ardb.h
 F:	configs/ls2080ardb_defconfig
 F:	configs/ls2080ardb_nand_defconfig
 
+LS2088A_QSPI-boot BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2088ardb_qspi_defconfig
+
+LS2081ARDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2081ardb_defconfig
+
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
 S:	Maintained