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Commits on Nov 9, 2017

• Merge pull request chipsalliance#1096 from freechipsproject/tools

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Commits on Nov 8, 2017

• Bump riscv-tools, for a new toolchain release

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Commits on Aug 8, 2017

• Merge pull request chipsalliance#933 from freechipsproject/cinst

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• Merge pull request chipsalliance#934 from freechipsproject/critical-paths

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• Print out the compressed instruction when executing one

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Commits on May 12, 2017

• Bump riscv-tools, to get some -mcmodel=medany fixes (chipsalliance#739)

  

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Commits on May 9, 2017

• Merge pull request chipsalliance#732 from ucb-bar/vectored-stvec

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Commits on Aug 5, 2016

• Add firrtl build dependencies

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Commits on Jul 12, 2016

• Fix the Nasti to Smi Converter for single-word Nasti busses

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Commits on Jun 16, 2016

• Don't build the Verilator man pages (chipsalliance#141)

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Commits on Jun 15, 2016

• Default to Chisel 3

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• Start testing Chisel 3 in Travis

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• Allow the regressions to run more than once

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• Install Verilator when building the emulator

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Commits on Jun 14, 2016

• Prevent sbt from running multiple times in emulator

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Commits on Jun 11, 2016

• Make a TileLink to Smi converter availiable to users (chipsalliance#136)

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Commits on Jun 10, 2016

• Use the new TileLink to Smi converter (#10)

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• Add a Smi to TileLink converter (chipsalliance#59)

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Commits on Jun 7, 2016

• Fix "make run-asm-tests" for Chisel 3

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Commits on Apr 19, 2016

• Merge pull request chipsalliance#90 from ucb-bar/elaborate-once

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Commits on Apr 18, 2016

• Bump Chisel3, to elaborate circuits once

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Commits on Mar 24, 2016

• Use Chisel 3 to build verilog on Travis

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• Add CHISEL_VERSION make argument

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• Correct the polarity of the non-backup-memory HTIF

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• Bump the uncore for some Chisel3 fixes

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• Fix the SCR file for Chisel 3

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• Move to a newer Scala version

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• Merge pull request chipsalliance#30 from ucb-bar/chisel3

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Commits on Mar 23, 2016

• Don't assign SInt(-1) to a UInt

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Commits on Mar 21, 2016

• Add cloneType methods for Chisel3

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• Fix the SCR file for Chisel 3

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• Fix the SCR file for Chisel 3

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Commits on Mar 15, 2016

• Work around Chisel3's lack of 0-width wires

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Commits on Mar 11, 2016

• Avoid right-shift by larger that the bit width

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• Avoid generating 0-width UInts

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