Fix narrow read/write behavior for AXI converters and fix L2 bugs

Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.

.travis.yml

@@ -50,6 +50,7 @@ env:
     - CONFIG=MemoryMuxMemtestConfig
     - CONFIG=BroadcastRegressionTestConfig
     - CONFIG=CacheRegressionTestConfig
+    - CONFIG=NastiConverterTestConfig
     - CONFIG=UnitTestConfig
     - CONFIG=SplitL2MetadataTestConfig
 

csrc/mm.cc

@@ -9,28 +9,30 @@
 
 void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size)
 {
+  strb &= ((1 << size) - 1) << (addr % word_size);
+
   if (addr > this->size) {
     fprintf(stderr, "Invalid write address %lx\n", addr);
     exit(EXIT_FAILURE);
   }
 
-  uint8_t *base = this->data + addr;
-  for (int i = 0; i < size; i++) {
+  uint8_t *base = this->data + (addr / word_size) * word_size;
+  for (int i = 0; i < word_size; i++) {
     if (strb & 1)
       base[i] = data[i];
     strb >>= 1;
   }
 }
 
-std::vector<char> mm_t::read(uint64_t addr, uint64_t size)
+std::vector<char> mm_t::read(uint64_t addr)
 {
   if (addr > this->size) {
     fprintf(stderr, "Invalid read address %lx\n", addr);
     exit(EXIT_FAILURE);
   }
 
   uint8_t *base = this->data + addr;
-  return std::vector<char>(base, base + size);
+  return std::vector<char>(base, base + word_size);
 }
 
 void mm_t::init(size_t sz, int wsz, int lsz)
@@ -81,19 +83,19 @@ void mm_magic_t::tick(
   bool b_fire = b_valid() && b_ready;
 
   if (ar_fire) {
-    uint64_t word_size = (1 << ar_size);
+    uint64_t start_addr = (ar_addr / word_size) * word_size;
     for (int i = 0; i <= ar_len; i++) {
-      auto dat = read(ar_addr + i * word_size, word_size);
+      auto dat = read(start_addr + i * word_size);
       rresp.push(mm_rresp_t(ar_id, dat, i == ar_len));
     }
   }
 
   if (aw_fire) {
     store_addr = aw_addr;
-    store_size = (1 << aw_size);
     store_id = aw_id;
-    store_inflight = true;
     store_count = aw_len + 1;
+    store_size = 1 << aw_size;
+    store_inflight = true;
   }
 
   if (w_fire) {

csrc/mm.h

@@ -7,9 +7,6 @@
 #include <cstring>
 #include <queue>
 
-void write_masked_data(
-    uint8_t *base, uint8_t *data, uint64_t strb, uint64_t size);
-
 class mm_t
 {
  public:
@@ -58,7 +55,7 @@ class mm_t
   virtual size_t get_line_size() { return line_size; }
 
   void write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size);
-  std::vector<char> read(uint64_t addr, uint64_t size);
+  std::vector<char> read(uint64_t addr);
 
   virtual ~mm_t();
 

csrc/mm_dramsim2.cc

@@ -18,8 +18,9 @@ using namespace DRAMSim;
 void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
 {
   auto req = rreq[address].front();
+  uint64_t start_addr = (address / word_size) * word_size;
   for (int i = 0; i < req.len; i++) {
-    auto dat = read(address + i * req.size, req.size);
+    auto dat = read(start_addr + i * word_size);
     rresp.push(mm_rresp_t(req.id, dat, (i == req.len - 1)));
   }
   rreq[address].pop();
@@ -84,15 +85,15 @@ void mm_dramsim2_t::tick(
   bool b_fire = b_valid() && b_ready;
 
   if (ar_fire) {
-    rreq[ar_addr].push(mm_req_t(ar_id, 1 << ar_size, ar_len + 1, ar_addr));
+    rreq[ar_addr].push(mm_req_t(ar_id, ar_len + 1, ar_addr));
     mem->addTransaction(false, ar_addr);
   }
 
   if (aw_fire) {
     store_addr = aw_addr;
-    store_size = (1 << aw_size);
     store_id = aw_id;
     store_count = aw_len + 1;
+    store_size = 1 << aw_size;
     store_inflight = true;
   }
 

csrc/mm_dramsim2.h

@@ -11,22 +11,19 @@
 
 struct mm_req_t {
   uint64_t id;
-  uint64_t size;
   uint64_t len;
   uint64_t addr;
 
-  mm_req_t(uint64_t id, uint64_t size, uint64_t len, uint64_t addr)
+  mm_req_t(uint64_t id, uint64_t len, uint64_t addr)
   {
     this->id = id;
-    this->size = size;
     this->len = len;
     this->addr = addr;
   }
 
   mm_req_t()
   {
     this->id = 0;
-    this->size = 0;
     this->len = 0;
     this->addr = 0;
   }

src/main/scala/TestBench.scala

@@ -300,15 +300,15 @@ object TestBenchGeneration extends FileSystemUtilities {
     begin
       if (ar_valid_$i && ar_ready_$i)
       begin
-        $$fdisplay(stderr, "MC$i: ar addr=%x", ar_addr_$i);
+        $$fdisplay(stderr, "MC$i: ar addr=%x size=%x", ar_addr_$i, ar_size_$i);
       end
       if (aw_valid_$i && aw_ready_$i)
       begin
-        $$fdisplay(stderr, "MC$i: aw addr=%x", aw_addr_$i);
+        $$fdisplay(stderr, "MC$i: aw addr=%x size=%x", aw_addr_$i, aw_size_$i);
       end
       if (w_valid_$i && w_ready_$i)
       begin
-        $$fdisplay(stderr, "MC$i: w data=%x", w_data_$i);
+        $$fdisplay(stderr, "MC$i: w data=%x strb=%x", w_data_$i, w_strb_$i);
       end
       if (r_valid_$i && r_ready_$i)
       begin

src/main/scala/TestConfigs.scala

@@ -142,7 +142,7 @@ class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig)
 class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new WithTraceGen ++ new GroundTestConfig)
 
 class FancyMemtestConfig extends Config(
-  new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++
+  new With2Cores ++ new With2MemoryChannels ++ new With4BanksPerMemChannel ++
   new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
 
 class MemoryMuxMemtestConfig extends Config(