Combine Coreplex and System Module Hierarchies (chipsalliance#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

Makefrag

@@ -4,7 +4,7 @@ $(error Please set environment variable RISCV. Please take a look at README)
 endif
 
 MODEL ?= TestHarness
-PROJECT ?= freechips.rocketchip.chip
+PROJECT ?= freechips.rocketchip.system
 CFG_PROJECT ?= $(PROJECT)
 CONFIG ?= DefaultConfig
 # TODO: For now must match rocketchip.Generator

README.md

@@ -156,9 +156,6 @@ Here is a brief description of what can be found in each package:
 
 * **amba**
 This RTL package uses diplomacy to generate bus implementations of AMBA protocols, including AXI4, AHB-lite, and APB.
-* **chip**
-This top-level utility package invokes Chisel to elaborate a particular configuration of a coreplex,
-along with the appropriate testing collateral.
 * **config**
 This utility package provides Scala interfaces for configuring a generator via a dynamically-scoped
 parameterization library.
@@ -188,6 +185,9 @@ This RTL package contains components that can be combined with cores to construc
 * **tilelink**
 This RTL package uses diplomacy to generate bus implementations of the TileLink protocol. It also contains a variety
 of adapters and protocol converters.
+* **system**
+This top-level utility package invokes Chisel to elaborate a particular configuration of a coreplex,
+along with the appropriate testing collateral.
 * **unittest**
 This utility package contains a framework for generateing synthesizeable hardware testers of individual modules.
 * **util**
@@ -291,11 +291,11 @@ verilator.
     DefaultConfig.graphml
     DefaultConfig.json
     DefaultConfig.memmap.json
-    freechips.rocketchip.chip.DefaultConfig
-    freechips.rocketchip.chip.DefaultConfig.d
-    freechips.rocketchip.chip.DefaultConfig.fir
-    freechips.rocketchip.chip.DefaultConfig.v
-    $ ls $ROCKETCHIP/emulator/generated-src/freechips.rocketchip.chip.DefaultConfig
+    freechips.rocketchip.system.DefaultConfig
+    freechips.rocketchip.system.DefaultConfig.d
+    freechips.rocketchip.system.DefaultConfig.fir
+    freechips.rocketchip.system.DefaultConfig.v
+    $ ls $ROCKETCHIP/emulator/generated-src/freechips.rocketchip.system.DefaultConfig
     VTestHarness__1.cpp
     VTestHarness__2.cpp
     VTestHarness__3.cpp
@@ -360,11 +360,11 @@ Top.DefaultConfig.conf file:
     DefaultConfig.graphml
     DefaultConfig.json
     DefaultConfig.memmap.json
-    freechips.rocketchip.chip.DefaultConfig.behav_srams.v
-    freechips.rocketchip.chip.DefaultConfig.conf
-    freechips.rocketchip.chip.DefaultConfig.d
-    freechips.rocketchip.chip.DefaultConfig.fir
-    freechips.rocketchip.chip.DefaultConfig.v
+    freechips.rocketchip.system.DefaultConfig.behav_srams.v
+    freechips.rocketchip.system.DefaultConfig.conf
+    freechips.rocketchip.system.DefaultConfig.d
+    freechips.rocketchip.system.DefaultConfig.fir
+    freechips.rocketchip.system.DefaultConfig.v
     $ cat $ROCKETCHIP/vsim/generated-src/*.conf
     name data_arrays_0_ext depth 512 width 256 ports mrw mask_gran 8
     name tag_array_ext depth 64 width 88 ports mrw mask_gran 22

regression/Makefile

@@ -42,17 +42,17 @@ $(error Set SUITE to the regression suite you want to run)
 endif
 
 ifeq ($(SUITE),RocketSuiteA)
-PROJECT=freechips.rocketchip.chip
+PROJECT=freechips.rocketchip.system
 CONFIGS=DefaultConfig
 endif
 
 ifeq ($(SUITE),RocketSuiteB)
-PROJECT=freechips.rocketchip.chip
+PROJECT=freechips.rocketchip.system
 CONFIGS=DefaultBufferlessConfig
 endif
 
 ifeq ($(SUITE),RocketSuiteC)
-PROJECT=freechips.rocketchip.chip
+PROJECT=freechips.rocketchip.system
 CONFIGS=TinyConfig
 endif
 

src/main/scala/amba/axi4/Test.scala

@@ -4,7 +4,7 @@ package freechips.rocketchip.amba.axi4
 
 import Chisel._
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.devices.tilelink.TLError
+import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.unittest._
@@ -98,7 +98,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
   val node = AXI4InputNode()
   val xbar = LazyModule(new TLXbar)
   val ram  = LazyModule(new TLRAM(fuzzAddr))
-  val error= LazyModule(new TLError(Seq(AddressSet(0x1800, 0xff))))
+  val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)))))
 
   ram.node   := TLFragmenter(4, 16)(xbar.node)
   error.node := TLFragmenter(4, 16)(xbar.node)