drivers: timer: infineon pdl lp_timer #97831

billwatersiii · 2025-10-17T21:10:43Z

Add PDL-based low-power timer for the E84 board

drivers/timer/ifx_cat1_lp_timer_pdl.c

billwatersiii · 2025-11-05T17:50:52Z

@andyross, @talih0, @teburd, please review this pull request.

teburd

I think there was some fundamental misunderstanding of how timers work in Zephyr when this was written, and I see it was mostly copied from the existing cat1-lp-timer driver and updated to the new HAL API if I understand this right. So likely both need fixing to correctly work.

This is maybe one of those few occasions where only the base address of the register block for the IP is needed and the few registers (typically 2-3..) are kept in C and Zephyr #define's rather than using the HAL.

dts/bindings/timer/infineon,cat1-lp-timer-pdl.yaml

teburd · 2025-11-05T19:00:32Z

drivers/timer/ifx_cat1_lp_timer_pdl.c

+		.clock_frequency = DT_INST_PROP(n, clock_frequency),                               \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, lptimer_init, NULL, &ifx_cat1_lptimer_data##n,                    \


No need to make the timer a device, its a singleton in Zephyr's view. Just a couple of static variables tied to the compilation unit for the hardware timer being used as the kernel timer.

Take a look at how cortex_m_systick.c is written for example. It sets up an initialization function with SYS_INIT and a few static variables tied to the compilation unit to stash some state (mostly the last announced tick or cycle count), along with the appropriate sys_clock functions implemented.

@teburd , Don't I need this for a multi-core device? Where each core has its own lptimer.

You can still use DT nodes and attributes, but you don't need to deal with struct device.

There's other multicore devices in the tree to peruse on how they might go about this. See NXP's RT1170 for example of an AMP design. But yes, each AMP core running an instance of Zephyr needs its own timer. In SMP this isn't the case, a single timer is expected.

@teburd , I am not finding "NXP's RT1170". Can you point me to it?

See for example mcux lptmr https://github.com/zephyrproject-rtos/zephyr/blob/main/drivers/timer/mcux_lptmr_timer.c

@teburd, the driver should now be updated to this flow.

drivers/timer/ifx_cat1_lp_timer_pdl.c

teburd · 2025-11-05T19:43:43Z

drivers/timer/ifx_cat1_lp_timer_pdl.c

+
+	lptimer_value = Cy_MCWDT_GetCount(config->reg_addr, CY_MCWDT_COUNTER2);
+
+	/* Gives the value of LPTIM counter (ms) since the previous 'announce' */


This is the number of elapsed kernel ticks (kernel ticks are a synthesized clock running at SYS_CLOCK_TICKS_PER_SEC) since the last announce call was made. So I think there's a misunderstanding below in the math.

What you want is something that converts delta_cycles to delta_ticks where each tick is equal to some number of cycles.

E.g.

uint32_t delta_cycles = current_cycle_count - announced_cycle_count; uint32_t delta_ticks = delta_cycles/cycles_per_tick; return delta_ticks;

However, some special care typically needs to happen for rollovers and things like this.

teburd · 2025-11-05T19:47:15Z

drivers/timer/ifx_cat1_lp_timer_pdl.c

+	}
+
+	/* Set the delay value for the next wakeup interrupt */
+	lptimer_set_delay(lptimer_dev, ((uint32_t)(ticks)*config->clock_frequency) /


This should be setting the counter compare register to some cycle count into the future based on ticks*cycles_per_tick, like...

uint32_t timer_compare = current_cycle_count + ticks*cycles_per_tick; sys_write32(SOME_TIMER_REG, timer_compare);

With some protection around short timeouts (usually some minimum cycle delay), and error checking for rollovers

I forgot to mention that the timer compare should also be tick aligned or the timer may trigger early which is an error. Meaning timer_compare % cycles_per_tick == 0 && timer_compare >= (cycle_count + ticks*cycles_per_tick) should be true or a programming error has occurred. The assertion above assumes no rollover which is possible.

drivers/timer/ifx_cat1_lp_timer_pdl.c

teburd · 2025-11-05T19:57:24Z

drivers/timer/ifx_cat1_lp_timer_pdl.c

+	if ((data->isr_instruction & LPTIMER_ISR_CALL_USER_CB_MASK) != 0) {
+		/* announce the elapsed time in ms */
+		uint32_t lptimer_value = Cy_MCWDT_GetCount(config->reg_addr, CY_MCWDT_COUNTER2);
+		int32_t delta_ticks = ((uint64_t)(lptimer_value - last_lptimer_value) *


This math is also not quite right. It should be something like...

uint32_t current_cycle_count = sys_read32(SOME_TIMER_COUNT_REG); uint32_t delta_ticks = (current_cycle_count - announced_cycle_count)/cycles_per_tick; announced_cycle_count = delta_ticks*cycles_per_tick; sys_clock_announce(....);

billwatersiii · 2025-11-05T20:17:30Z

I think there was some fundamental misunderstanding of how timers work in Zephyr when this was written, and I see it was mostly copied from the existing cat1-lp-timer driver and updated to the new HAL API if I understand this right. So likely both need fixing to correctly work.

This is maybe one of those few occasions where only the base address of the register block for the IP is needed and the few registers (typically 2-3..) are kept in C and Zephyr #define's rather than using the HAL.

@teburd , you are correct, this is just a port of the existing driver from using the HAL to the PDL. Thanks for your feedback. I will work on that now.

mcatee-infineon · 2025-12-09T21:22:53Z

Rebasing PR onto main

Add PDL-based low-power timer for the E84 board Signed-off-by: Bill Waters <bill.waters@infineon.com>

mcatee-infineon · 2025-12-11T00:53:14Z

@teburd. This PR has been updated with refactoring akin to that done in #99689

sonarqubecloud · 2025-12-11T01:20:31Z

Quality Gate passed

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zephyrbot added area: Devicetree Bindings platform: Infineon Infineon Technologies AG area: Timer Timer area: Boards/SoCs labels Oct 17, 2025

zephyrbot requested review from andyross, mcatee-infineon, sreeramIfx, talih0 and teburd October 17, 2025 21:12

zephyrbot assigned sreeramIfx Oct 17, 2025

billwatersiii force-pushed the ifx_pdl_lp_timer branch from 90e628b to fcc5925 Compare October 17, 2025 21:21

sreeramIfx added this to the v4.3.0 milestone Oct 21, 2025

billwatersiii mentioned this pull request Oct 21, 2025

soc: infineon: add pse84 power management #98036

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sreeramIfx reviewed Oct 24, 2025

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billwatersiii force-pushed the ifx_pdl_lp_timer branch from fcc5925 to c5d6069 Compare October 24, 2025 23:13

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sreeramIfx modified the milestones: v4.3.0, v4.4.0 Oct 30, 2025

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billwatersiii force-pushed the ifx_pdl_lp_timer branch from c5d6069 to 4973287 Compare November 7, 2025 19:16

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billwatersiii force-pushed the ifx_pdl_lp_timer branch 3 times, most recently from 25be703 to b938b87 Compare November 21, 2025 19:48

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mcatee-infineon force-pushed the ifx_pdl_lp_timer branch from 98fd223 to 927df19 Compare December 10, 2025 00:03

drivers: timer: infineon pdl lp_timer

2ff73a7

Add PDL-based low-power timer for the E84 board Signed-off-by: Bill Waters <bill.waters@infineon.com>

mcatee-infineon force-pushed the ifx_pdl_lp_timer branch from 927df19 to 2ff73a7 Compare December 11, 2025 00:53


		lptimer_value = Cy_MCWDT_GetCount(config->reg_addr, CY_MCWDT_COUNTER2);

		/* Gives the value of LPTIM counter (ms) since the previous 'announce' */

drivers: timer: infineon pdl lp_timer #97831

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drivers: timer: infineon pdl lp_timer #97831

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