i2c: i2c_ll_stm32_v2: fix NACK handling for STM32L4 #7626
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## master #7626 +/- ##
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+ Coverage 55.31% 55.32% +<.01%
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Files 470 470
Lines 51913 51913
Branches 9923 9923
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+ Misses 19270 19269 -1
Partials 3925 3925
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ydamigos
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ydamigos
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Actually, NACK is an I2C event interrupt for all series supported by i2c_ll_stm32_v2. We just need to move NACK handling code to event ISR.
On STM32F0/F3/L0/L4, a NACK on the I2C bus triggers an I2C event interrupt. But the current logic expects an I2C error interrupt. As a result, the NACK interrupt is not acknowledged and leads to an IRQ storm which freezes the system. Move the NACK handling code to the event ISR. Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
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Indeed, this is the case on STM32F0/F3/L0/L4. I moved the NACK handling to the event ISR and updated the commit message accordingly. |
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Now that we handle NACK in event ISR the |
| data->current.is_nack = 1; | ||
| } else { | ||
| data->current.is_err = 1; | ||
| } |
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This does not seem to be in the right place in the event handler, it should be handled before looking at the message it self.
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@vaussard Here is the Linux implementation of the same IP (STM32F7 uses the same i2c IP) https://github.com/torvalds/linux/blob/master/drivers/i2c/busses/i2c-stm32f7.c#L670
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Indeed, commit 81cfdec should also fixe the issue. Closing this PR, I did not had a lot of time to work on it anyway. |
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On STM32L4, a NACK on the I2C bus triggers an I2C event interrupt (see
for example Figure 420 in the STM32L4x6 TRM). But the current logic
expects an I2C error interrupt. As a result, the NACK interrupt is
not acknowledged and leads to an IRQ storm which freezes the system.
Factorize the NACK handling code to share it between event and error
ISRs, then call it from the event ISR if we compile for STM32L4.