Add Zephyr RTOS support for WCH CH32V003 #73761

kholia · 2024-06-05T05:31:32Z

Details

This PR adds Zephyr RTOS support for WCH CH32V003 RISC-V MCU.

https://www.wch-ic.com/products/CH32V003.html

Usage

west update

west build -p always -b wch_ch32v003evt samples/basic/blinky

west flash -r minichlink

Tested On

Bare CH32V003J4M6 SOP-8 chip
WCH CH32V003EVT board (CH32V003 Evaluation Kit)

Blinky Build

$ west build -p always -b wch_ch32v003evt samples/basic/blinky
...
-- Zephyr version: 3.6.99 (zephyr), build: v3.6.0-5403-g90b43c51ff3f
[101/101] Linking C executable zephyr/zephyr.elf
Memory region         Used Size  Region Size  %age Used
             ROM:       10056 B        16 KB     61.38%
             RAM:        1524 B         2 KB     74.41%
        IDT_LIST:          0 GB         2 KB      0.00%
Generating files from zephyr/build/zephyr/zephyr.elf for board: wch_ch32v003evt

It is fun to see Zephyr RTOS running on a "10 cent" MCU.

github-actions · 2024-06-05T05:32:11Z

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zephyrbot · 2024-06-05T05:32:22Z

The following west manifest projects have been modified in this Pull Request:

Name	Old Revision	New Revision	Diff
hal_wch	N/A	zephyrproject-rtos/hal_wch@`1de9d3e` (main)	N/A

Note: This message is automatically posted and updated by the Manifest GitHub Action.

soc/wch/ch32v00x/Kconfig

soc/wch/ch32v00x/soc.yml

soc/wch/ch32v00x/Kconfig.soc

boards/wch/ch32v003evt/Kconfig

boards/wch/ch32v003evt/Kconfig.board

boards/wch/ch32v003evt/Kconfig.defconfig

dts/bindings/pinctrl/wch,afio.yaml

drivers/gpio/Kconfig.ch32v00x

cnlohr · 2024-10-07T18:59:08Z

@kholia do you have a summary for what you changed? Or who's if any's quests have been changed?

kholia · 2024-10-08T02:21:43Z

@cnlohr I just added select ATOMIC_OPERATIONS_C line and rebased the PR on top of latest upstream main.

The current build failure does NOT seem related to this work.

I will rebase and re-push the commits.

kholia · 2024-10-09T07:38:28Z

I have rebased and re-pushed the same commits in the hope of passing the CI checks!

The current situation about CH32V307 header files licensing got a bit confusing, and this is an attempt to sort things out. Originally the WCH BSP files coming from the initial CH32V307 port commit came with an Apache 2.0 licence, which then it disappeared from newer BSP file versions. However, this prevented other projects such as Zephyr to actually support this MCU (and others from the same family). This prompted a request to WCH to relicense the BSP files under a more permissive licence such as MIT. A specific set of headers is currently available under the MIT licence after explicit relicensing from WCH, which is what this commit adds as a submodule. For reference, see openwch/ch32v003#45 and zephyrproject-rtos/zephyr#73761 (comment) Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

cnlohr · 2024-10-11T21:43:22Z

There are still 4 changes requested - are they just waiting to be checked off by those reviewers? I wonder if someone should/could ping them?

cfriedt

I didn't manage to finish my last review. Just a small suggestion - not sure if it's still relevant

cfriedt · 2024-10-09T12:57:35Z

drivers/clock_control/clock_control_wch_rcc.c

+	RCC_TypeDef *regs = config->regs;
+	uint8_t id = (uintptr_t)sys;
+
+	*(&regs->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id)) |= 1 << WCH_RCC_CLOCK_ID_BIT(id);


Suggested change

*(&regs->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id)) |= 1 << WCH_RCC_CLOCK_ID_BIT(id);

sys_write32(BIT(WCH_RCC_CLOCK_ID_BIT(id), &regs->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id));

This results in:

clock_control_wch_rcc.c:31:68: warning: passing argument 2 of 'sys_write32' makes integer from pointer without a cast [-Wint-conversion] 31 | sys_write32(BIT(WCH_RCC_CLOCK_ID_BIT(id)), &regs->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id)); | ^ | | | volatile uint32_t * {aka volatile unsigned int *}

Does the following change make sense?

+#define ENABLE_RCC_CLOCK(regs, id) \ + (*(&(regs)->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id)) |= BIT(WCH_RCC_CLOCK_ID_BIT(id))) + #define WCH_RCC_CLOCK_ID_OFFSET(id) (((id) >> 5) & 0xFF) #define WCH_RCC_CLOCK_ID_BIT(id) ((id) & 0x1F) @@ -28,7 +31,8 @@ static int clock_control_wch_rcc_on(const struct device *dev, clock_control_subs RCC_TypeDef *regs = config->regs; uint8_t id = (uintptr_t)sys; - *(&regs->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id)) |= 1 << WCH_RCC_CLOCK_ID_BIT(id); + ENABLE_RCC_CLOCK(regs, id);

nzmichaelh · 2024-10-12T14:32:07Z

Looking forward to this landing! Here's a short video of 5 CH32V003 based boards running Zephyr and at least blinking a LED: https://juju.nz/michaelh/post/2024/all_so_far/

Once this PR lands, I'll send through PRs for I2C, SPI, and other drivers.

cfriedt · 2024-10-12T18:30:39Z

Looking forward to this landing! Here's a short video of 5 CH32V003 based boards running Zephyr and at least blinking a LED: https://juju.nz/michaelh/post/2024/all_so_far/

Awesome! 🪁

nordicjm · 2024-10-14T06:23:25Z

soc/wch/ch32v00x/Kconfig.defconfig

+config PINCTRL
+	default y


Not allowed, drivers must select this

Roger.

A bunch of existing code is doing the same thing though.

$ cat soc/atmel/sam/Kconfig.defconfig # Atmel SAM MCU family default configuration options # Copyright (c) 2016 Piotr Mienkowski # Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com> # SPDX-License-Identifier: Apache-2.0 if SOC_FAMILY_ATMEL_SAM rsource "*/Kconfig.defconfig" config CLOCK_CONTROL default y config GPIO default y config PINCTRL default y config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config WATCHDOG default y endif # SOC_FAMILY_ATMEL_SAM

Also there are other examples:

$ rg "config PINCTRL" | grep soc soc/infineon/cat3/Kconfig.defconfig:config PINCTRL soc/nxp/imxrt/Kconfig.defconfig:config PINCTRL_IMX soc/microchip/mec/mec175x/Kconfig.defconfig.mec1753qlj:config PINCTRL soc/microchip/mec/mec175x/Kconfig.defconfig.mec1753qsz:config PINCTRL soc/microchip/mec/mec174x/Kconfig.defconfig.mec1743qsz:config PINCTRL soc/microchip/mec/mec174x/Kconfig.defconfig.mec1743qlj:config PINCTRL soc/microchip/mec/mech172x/Kconfig.defconfig.mech1723nlj:config PINCTRL soc/microchip/mec/mech172x/Kconfig.defconfig.mech1723nsz:config PINCTRL soc/gd/gd32/Kconfig.defconfig:config PINCTRL soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_a53:config PINCTRL_IMX soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_m7:config PINCTRL_IMX soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq6_m4:config PINCTRL_IMX soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn6_a53:config PINCTRL_IMX soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm6_m4:config PINCTRL_IMX soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm6_a53:config PINCTRL_IMX soc/nxp/imx/imx7d/Kconfig.defconfig:config PINCTRL_IMX soc/nxp/imx/imx6sx/Kconfig.defconfig:config PINCTRL_IMX soc/nxp/imx/imx9/imx93/Kconfig.defconfig.mimx93.a55:config PINCTRL_IMX soc/ti/k3/am6x/Kconfig.defconfig:config PINCTRL soc/ite/ec/it8xxx2/Kconfig.defconfig.series:config PINCTRL soc/atmel/sam/Kconfig.defconfig:config PINCTRL soc/atmel/sam0/Kconfig.defconfig:config PINCTRL soc/wch/ch32v00x/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra6m5/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra6e2/Kconfig.defconfig:config PINCTRL soc/raspberrypi/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra4m3/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra8m1/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra6e1/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra2a1/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra8d1/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra6m3/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra6m2/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra8t1/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra6m1/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra4w1/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra4e2/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra6m4/Kconfig.defconfig:config PINCTRL soc/renesas/ra/ra4m2/Kconfig.defconfig:config PINCTRL soc/telink/tlsr/tlsr951x/Kconfig.defconfig:config PINCTRL soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0:config PINCTRL soc/renesas/rcar/rcar_gen3/Kconfig.defconfig:config PINCTRL

nzmichaelh · 2024-10-20T14:51:03Z

@kholia I noticed a bug in the GPIO input mode configuration code. See nzmichaelh@e32d9ac for a fix that also adds pullup / pulldown support.

This is used for WCH chips including the CH32V003. Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds the dtsi and bindings for the WCH CH32V003 which is a 32-bit general-purpose RISC-V MCU. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds the soc support for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds the pinctrl driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds the clock driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds the systick driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds the usart driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds the pfic interrupt controller driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds the gpio driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds support for the CH32V003EVT board which features a 32-bit general-purpose RISC-V MCU. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

This commit adds a runner wrapper for the 'minichlink' program which offers a free, open mechanism to use the CH-LinkE programming dongle for the CH32V003. https://github.com/cnlohr/ch32v003fun/tree/master/minichlink Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

kholia · 2024-10-20T15:35:53Z

@kholia I noticed a bug in the GPIO input mode configuration code. See nzmichaelh@e32d9ac for a fix...

Applied and pushed - thanks!

zhang-wenchao · 2024-10-22T08:03:07Z

I have purchased the WCH board and can't wait to run Zephyr on it. What is I can do? Help to accelerate the merger.

kholia requested review from dcpleung and nashif as code owners June 5, 2024 05:31

zephyrbot added area: Timer Timer area: Clock Control area: Interrupt Controller area: GPIO area: RISCV RISCV Architecture (32-bit & 64-bit) area: Devicetree Binding PR modifies or adds a Device Tree binding area: West West utility area: Pinctrl labels Jun 5, 2024

zephyrbot added manifest manifest-hal_wch labels Jun 5, 2024

zephyrbot requested review from andyross, carlescufi, decsny, fkokosinski, galak, gmarull, henrikbrixandersen and kgugala June 5, 2024 05:32

zephyrbot added the DNM This PR should not be merged (Do Not Merge) label Jun 5, 2024

zephyrbot requested review from mbolivar-ampere, mnkp, nordic-krch, swinslow and teburd June 5, 2024 05:32

zephyrbot assigned galak Jun 5, 2024

nordicjm requested changes Jun 5, 2024

View reviewed changes

kholia force-pushed the ch32v003-for-upstream branch 2 times, most recently from 39630a6 to 2ca52da Compare October 7, 2024 03:24

zephyrbot added the DNM This PR should not be merged (Do Not Merge) label Oct 7, 2024

kholia force-pushed the ch32v003-for-upstream branch 2 times, most recently from f87099a to aa19307 Compare October 9, 2024 07:37

cfriedt reviewed Oct 11, 2024

View reviewed changes

nordicjm requested changes Oct 14, 2024

View reviewed changes

kholia and others added 11 commits October 20, 2024 21:04

west: add the hal_wch

e52b096

This is used for WCH chips including the CH32V003. Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

dts: add the ch32v003 dtsi

1df39f4

This commit adds the dtsi and bindings for the WCH CH32V003 which is a 32-bit general-purpose RISC-V MCU. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

soc: add wch_ch32v003 soc files

be5945c

This commit adds the soc support for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

drivers: add ch32v00x pinctrl support

62e7941

This commit adds the pinctrl driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

drivers: add the ch32v00x clock controller

8807c9f

This commit adds the clock driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

drivers: add the ch32v00x systick driver

6db6824

This commit adds the systick driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

drivers: add the ch32v00x usart driver

cb9098e

This commit adds the usart driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

drivers: add the pfic interrupt controller

a839c36

This commit adds the pfic interrupt controller driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

drivers: add the gpio driver for wch ch32v003

3a7c34f

This commit adds the gpio driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

boards: add ch32v003evt

d26dff2

This commit adds support for the CH32V003EVT board which features a 32-bit general-purpose RISC-V MCU. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

kholia force-pushed the ch32v003-for-upstream branch from aa19307 to 88e6d57 Compare October 20, 2024 15:35

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Add Zephyr RTOS support for WCH CH32V003 #73761

Add Zephyr RTOS support for WCH CH32V003 #73761

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zhang-wenchao commented Oct 22, 2024

	*(&regs->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id)) \|= 1 << WCH_RCC_CLOCK_ID_BIT(id);
	sys_write32(BIT(WCH_RCC_CLOCK_ID_BIT(id), &regs->AHBPCENR + WCH_RCC_CLOCK_ID_OFFSET(id));

Add Zephyr RTOS support for WCH CH32V003 #73761

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kholia commented Jun 5, 2024 • edited Loading

Details

Usage

Tested On

Blinky Build

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