Add support for SOPHGO SoCs and Milk-V boards #69594
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T-Head is a semiconductor chip business entity of Alibaba Group. Signed-off-by: Chen Xingyu <hi@xingrz.me>
SOPHGO is a company focus on development of TPU and RISC-V processors. Signed-off-by: Chen Xingyu <hi@xingrz.me>
MilkV is a RISC-V MCU company located in Shenzhen, China. Signed-off-by: Chen Xingyu <hi@xingrz.me>
C906 is a RISC-V CPU designed by T-Head. This commit introduces its DTS binding for later use. Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit adapts the existing RISC-V Machine Timer driver to support the T-Head C906 core, which lacks a standard memory-mapped `MTIME` register. Changes include: * Added `mtime-is-32bits` and `mtimecmp-is-32bits` properties to support SoCs where `MTIME`/`MTIMECMP` must be accessed as two separate 32-bit registers, even on 64-bit platforms. * Added `mtime-is-csr` property to allow reading the timer value from the `time` CSR instead of a memory-mapped `MTIME` register. * Made the `MTIME` register address optional in DTS; register addresses are now resolved by `reg-names` instead of relying on index position. Signed-off-by: Chen Xingyu <hi@xingrz.me>
CV180x is a series of RV64 SoCs developed by SOPHGO (formerly CVITEK), based on T-Head C906 CPU. Co-authored-by: honglin leng <a909204013@gmail.com> Signed-off-by: Chen Xingyu <hi@xingrz.me>
SG2000, also named "CV1813H". SG2002, also named "CV1812CP". Both of them are multi-core SoCs developed by SOPHGO, belonging to the CV181x series. Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit introduces a pin-controller driver for the CVI series SoCs by SOPHGO. Predefined pinmux values are also added. Please refer to the official datasheet for the naming conventions of pins and signals. Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit adds PWM driver for CVI series SoCs. Signed-off-by: Chen Xingyu <hi@xingrz.me>
This implements a mailbox driver for CV18xx, a series of multi-core SoCs by SOPHGO. This driver enables the little core of CV18xx running RTOS to communicate with its big core running Linux. Signed-off-by: honglin leng <a909204013@gmail.com> Signed-off-by: Chen Xingyu <hi@xingrz.me>
The SOPHGO CVI series SoCs load the RTOS kernel for the 2nd core from a `fip.bin` located in the main storage. This commit introduced a convenient script for updating the `fip.bin` on the external storage mounted to the host, with the newly built `zephyr.bin`. Path to the `fiptool.py` from the official SDK should be provided. Signed-off-by: Chen Xingyu <hi@xingrz.me>
Milk-V Duo is a tiny development board shipped with SOPHGO CV1800B. Signed-off-by: Chen Xingyu <hi@xingrz.me>
Duo S is another development board by Milk-V, shipped with SOPHGO SG2000. Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit adds an overlay to the PWM driver tests for Milk-V boards. Signed-off-by: Chen Xingyu <hi@xingrz.me>
Also added @lenghonglin as collaborator Signed-off-by: Chen Xingyu <hi@xingrz.me>
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@VynDragon @fkokosinski @henrikbrixandersen Hi, could you please go back again take a look since all CI checks have passed and all dependencies has merged. I think it's time to move forward. |
There are still some comments that weren't addressed. Anyway I have some questions @xingrz: |
The RAM region is defined in the board DTS, since the available memory is configurable and varies between boards. As for flash: since Zephyr is always loaded into the second core by the BL and doesn’t run in XIP mode, I haven’t defined a flash region. |
Ah and it runs from the same ram zone, okay, thank you. |
| config SYS_CLOCK_HW_CYCLES_PER_SEC | ||
| default 25000000 |
There was a problem hiding this comment.
this needs to come from a DTS value
| default 25000000 | ||
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| config NUM_IRQS | ||
| int |
| config SYS_CLOCK_HW_CYCLES_PER_SEC | ||
| default 25000000 | ||
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| config SYS_CLOCK_HW_CYCLES_PER_SEC | ||
| default 25000000 | ||
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| config NUM_IRQS | ||
| int | ||
| default 128 |
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@xingrz Will you be interested in also porting zephyr to core 0? I got my duo booting on NOR flash (DIP-8 W25Q64FV 🤣 ) for quick development and to have cklink jtag as well from there, zephyr bin can replace bl2.bin in fiptool and do the exact same ops easily and continue on without the need for sdcard or OS build. |
@VynDragon That’s cool! But I’d prefer to keep this PR simple and focused, and leave that for someone to explore in the future. |
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Of course, I meant past this PR, eg do you intend to continue development for this SoC and/or add support for zephyr on first core, or is it only submitting/up to the sophgo riscv hackaton thing's objectives? |
This PR ports Zephyr to SOPHGO platforms, including 3 new SoCs and 2 boards:
milkv_duo/cv1800b/c906_1milkv_duo/sg2002/c906_1milkv_duos/sg2002/c906_1The CV1800B is a member of the SOPHGO CV180X series. It's a multi-core RV64 SoC, consists with a 1GHz T-Head C906 RV64 big core running Linux, and a 700MHz C906 RV64 little core running RTOS.
The SG2000/SG2002 is a successor of CV1800B, belonging to the CV181x series. It features a 1GHz ARM Cortex-A53 big core, a 1GHz T-Head C906 RV64 big core, and a 700MHz C906 RV64 little core.
This PR uses the
cpuclustersfield introduced by HWMv2 to distinguish between different cores within SOPHGO SoCs. The core names are based on SOPHGO’s official Technical Programming Manual (TPM):a53c906_0c906_1This PR brings Zephyr support to the C906 little core (the coprocessor), and lays the groundwork for future support of the A53/C906 big cores.
TODOs
DT_INST_IRQN_BY_IDX#69650size_tformatting with%.*s#81626size_tformatting withPRIu16#81803