Stm32f1 spi #5506
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Stm32f1 spi #5506
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Like other STM SoCs (L4 and F0), switch the flash registers struct to volatile. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the missing Flash properties in the STM32F0 dtsi. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Fix to the correct flash page size for the stm32f030x8 SoC. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the STM32F0 Embedded Flash support in the flash_stm32 driver interface. The STM32F0 has a particularity or use the HSI as clock source for the flash controller interface, so this clock must be enabled directly in the case HSE or another clock is used by the system clock. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Enable USB OTG support for olimex stm32-e407 and stm32f407g_disc1 boards by adding USB OTG to the pinmux table. Also, fix out of range endpoint addresses in CDC ACM case for STM32F4 based boards. Signed-off-by: Sudarsana Nagineni <sudarsana.nagineni@intel.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The STM32F0 has only a single IRQ line, add a combined IRQ handler. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
On stm32f3_disco pins PF0/PF1 are used for OSC_IN/OSC_OUT signals. Use pins PA9/PA10 for I2C_2 port Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Jonas Pfaff <jonas.pfaff@gmail.com>
Build the STM32Cube LL SPI Code for STM32F0 Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Include the STM32Cube LL SPI Header for STM32F0 Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add support for STM32F0 similar to STM32F3 and STM32L4 Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Current implementation of LL_SPI_TransmitData16 on F0 family generates following warning: "warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]" Besides being forbidden by rule, this cast is not needed, as register is 16 bits wide. Modification has been tested on F0 SoC. stm32yyxx_ll_spi.h being included in soc.h file, warning is generated at each compiled object, this commit allows a clean build. This issue is referenced in ST and tracked under reference 13359. Code will be updated on upcoming stm32cube updates. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the SPI1 and SPI2 pinmux for the nucleo_f091rc board Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Enable spi_loopback test to work with the nucleo_f091rc board using the SPI1 controller Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add STM32F0 Pinmuxes for SPI1 and SPI2 controllers to be used on the nucleo_f091rc board. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The combination of CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL and CONFIG_CLOCK_STM32_PLL_SRC_HSI on SOCs with PREDIV1 support made use of the LL define LL_RCC_PLLSOURCE_HSI_DIV_2, which is not defined for SOCs with PREDIV1 support. This exchanges LL_RCC_PLLSOURCE_HSI_DIV_2 with LL_RCC_PLLSOURCE_HSI which is the appropiate source according to stm32f0xx_ll_rcc.h line 473 and stm32f3xx_ll_rcc.h line 795. Tested by compiling hello world for nucleo_f091rc board with HSI as PLLSOURCE. Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
STM32 UART driver uses a macro for clock initialization, that is difficult to read and incompatible with needed changes to fix STM32F0 series UART problems. This change switches to using the full clock bus names in UART init functions removing the macro-magic and increasing readability. Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
STM32F0 Series uses different clock busses for UARTs than other STM32FX Series. fixes zephyrproject-rtos#5406 Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
Enables SPI driver for STM32F1 SoCs Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
TX/RX buffer may be NULL, so check them before use. Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Substitute null rx buffers with dummy rx buffers. Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
dsfgdsfgsdfgdfgdf
requested review from
SebastianBoe,
dbkinder,
erwango,
mbolivar,
nashif and
tbursztyka
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dbkinder
approved these changes
Dec 29, 2017
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+1 for docs, but looks like shippable build failures and marge conflicts need resolution
Contributor
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@dsfgdsfgsdfgdfgdf this PR is a duplicate of PR #5413, rebased against the master branch. Did you create it by mistake? |
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@@dsfgdsfgsdfgdfgdf, if confirmed this is a mistake, can we close this? |
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