Skip to content

Conversation

stephanosio
Copy link
Member

@stephanosio stephanosio commented Aug 1, 2022

This commit updates the custom target architecture type specified for
the SOC_OPENISA_RV32M1_RI5CY and SOC_OPENISA_RV32M1_ZERO_RISCY SoC
types to be compatible with the GCC 12, which now uses the ISA spec
20191213 by default.

Note that the hack overriding the build system-default -march flag
for these SoCs needs to be removed and they should be properly
specified using the ISA extension Kconfigs.

Signed-off-by: Stephanos Ioannidis root@stephanos.io

NOTE: To be merged after Zephyr SDK 0.15.0 is mainlined.

This commit updates the custom target architecture type specified for
the `SOC_OPENISA_RV32M1_RI5CY` and `SOC_OPENISA_RV32M1_ZERO_RISCY` SoC
types to be compatible with the GCC 12, which now uses the ISA spec
20191213 by default.

Note that the hack overriding the build system-default `-march` flag
for these SoCs needs to be removed and they should be properly
specified using the ISA extension Kconfigs.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Copy link
Contributor

@carlocaione carlocaione left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

:( LGTM but ugly

@mbolivar-nordic
Copy link
Contributor

I'm not touching this board anymore; I upstreamed support for it as a contract worker at a previous job, and studiously avoided volunteering to maintain it ;).

@stephanosio stephanosio marked this pull request as ready for review August 25, 2022 13:39
@stephanosio stephanosio requested a review from dleach02 as a code owner August 25, 2022 13:39
@zephyrbot zephyrbot added the area: RISCV RISCV Architecture (32-bit & 64-bit) label Aug 25, 2022
@stephanosio
Copy link
Member Author

To be merged as part of #49496

@stephanosio stephanosio added the DNM This PR should not be merged (Do Not Merge) label Aug 25, 2022
@stephanosio
Copy link
Member Author

Merged as part of #49496

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

area: RISCV RISCV Architecture (32-bit & 64-bit) DNM This PR should not be merged (Do Not Merge)

Projects

None yet

Development

Successfully merging this pull request may close these issues.

6 participants