Skip to content

riscv: MTVAL CSR not supported on OpenISA RV32M1 #34077

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Apr 8, 2021
Merged

riscv: MTVAL CSR not supported on OpenISA RV32M1 #34077

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 7 additions & 1 deletion arch/riscv/core/fatal.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,15 +103,21 @@ void _Fault(z_arch_esf_t *esf)
}
}
#endif /* CONFIG_USERSPACE */
ulong_t mcause, mtval;
ulong_t mcause;

__asm__ volatile("csrr %0, mcause" : "=r" (mcause));

#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
ulong_t mtval;
__asm__ volatile("csrr %0, mtval" : "=r" (mtval));
#endif

mcause &= SOC_MCAUSE_EXP_MASK;
LOG_ERR("");
LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
LOG_ERR(" mtval: %lx", mtval);
#endif

z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf);
}
Expand Down