tests/subsys/usb/bos/ fails randomly

[aescolar]

tests/subsys/usb/bos/ relies on the linker placing the cap_webusb and cap_msosv2 structures in that order in between __usb_bos_desc_start and __usb_bos_desc_end. But the linker will order them at will.
This causes the test to fail when this order does not match the expected one.
For example in an actual compile & run:

0804fd2c D __usb_bos_desc_start
0804fd31 d cap_msosv2
0804fd4d d cap_webusb
0804fd65 D __usb_bos_desc_end

***** Booting Zephyr OS v1.9.0-5866-g5aa09c6 *****
Running test suite test_osdesc
===================================================================
starting test - test_usb_bos_macros
length 57
00000000 05 0f 39 00 02 1c 10 05  00 df 60 dd d8 89 45 c7 
00000010 4c 9c d2 65 9d 9e 64 8a  9f 00 00 03 06 03 00 02 
00000020 00 18 10 05 00 38 b6 08  34 a9 09 a0 47 8b fd a0 
00000030 76 88 15 b6 65 00 01 01  01 
00000000 05 0f 39 00 02 18 10 05  00 38 b6 08 34 a9 09 a0 
00000010 47 8b fd a0 76 88 15 b6  65 00 01 01 01 1c 10 05 
00000020 00 df 60 dd d8 89 45 c7  4c 9c d2 65 9d 9e 64 8a 
00000030 9f 00 00 03 06 03 00 02  00 

    Assertion failed at [..]/tests/subsys/usb/bos/src/test_bos.c:205: test_usb_bos_macros: (!memcmp(hdr, &webusb_bos_descriptor, len) is false)
Wrong data
FAIL - test_usb_bos_macros
===================================================================
starting test - test_usb_bos
test_usb_bos: ret 0 len 57 data 0x0805c24c

    Assertion failed at [..]/tests/subsys/usb/bos/src/test_bos.c:226: test_usb_bos: (!memcmp(data, &webusb_bos_descriptor, len) is false)
Wrong data
FAIL - test_usb_bos
===================================================================
===================================================================
PROJECT EXECUTION FAILED

[finikorg]

OK, I think we can have structure in 2 orders and compare both.