Doesn't compile if XCHAL_HAVE_ICACHE_DYN_WAYS and XCHAL_HAVE_DCACHE_DYN_WAYS are defined for an Xtensa processor

[zephyrbot]

Reported by Rajavardhan Gundi:

The macros XCHAL_HAVE_ICACHE_DYN_WAYS and XCHAL_HAVE_DCACHE_DYN_WAYS, if defined for a particular processor, would result in a failure in compilation throwing "undefined reference to __memctl_default'" and "undefined reference to _MemErrorHandler'".

We would need a sample implementation of these 2 functions in the zephyr "startup" directory.

(Imported from Jira ZEP-2268)

[rgundi]

This was fixed by introducing 2 new files memctl_default.S and memerror-vector.S.