STM32: I-cache & D-cache

[manoj153]

are these caches are enabled or disabled by zephyr for the STM32 MCU line?

By default, the instruction cache and the data cache are both disabled.
The Arm® CMSIS library provides two functions that enable data and instruction caches:
• SCB_EnableICache() to enable the instruction cache
• SCB_EnableDCache() to enable and invalidate the data cache

[erwango]

@manoj153 These are both enabled on STM32F7 and STM32H7 series.

[erwango]

Question answered