kconfig: remove Enable from boolean prompts

According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:

sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

Kconfig.zephyr

@@ -221,7 +221,7 @@ config SRAM_OFFSET
 menu "Linker Sections"
 
 config LINKER_USE_BOOT_SECTION
-	bool "Enable Usage of Boot Linker Section"
+	bool "Usage of Boot Linker Section"
 	help
 	  If enabled, the symbols which are needed for the boot process
 	  will be put into another linker section reserved for these
@@ -231,7 +231,7 @@ config LINKER_USE_BOOT_SECTION
 	  board or custom linker script.
 
 config LINKER_USE_PINNED_SECTION
-	bool "Enable Usage of Pinned Linker Section"
+	bool "Usage of Pinned Linker Section"
 	help
 	  If enabled, the symbols which need to be pinned in memory
 	  will be put into another linker section reserved for pinned
@@ -309,7 +309,7 @@ config NO_OPTIMIZATIONS
 endchoice
 
 config COMPILER_COLOR_DIAGNOSTICS
-	bool "Enable colored diagnostics"
+	bool "Colored diagnostics"
 	default y
 	help
 	  Compiler diagnostic messages are colorized.
@@ -349,7 +349,7 @@ config NO_RUNTIME_CHECKS
 	  Do not do any runtime checks or asserts when using the CHECK macro.
 
 config RUNTIME_ERROR_CHECKS
-	bool "Enable runtime error checks"
+	bool "Runtime error checks"
 	help
 	  Always perform runtime checks covered with the CHECK macro. This
 	  option is the default and the only option used during testing.

arch/Kconfig

@@ -378,7 +378,7 @@ config NOCACHE_MEMORY
 menu "Interrupt Configuration"
 
 config DYNAMIC_INTERRUPTS
-	bool "Enable installation of IRQs at runtime"
+	bool "Installation of IRQs at runtime"
 	help
 	  Enable installation of interrupts at runtime, which will move some
 	  interrupt-related data structures to RAM instead of ROM, and
@@ -436,7 +436,7 @@ config GEN_IRQ_START_VECTOR
 	  left alone.
 
 config IRQ_OFFLOAD
-	bool "Enable IRQ offload"
+	bool "IRQ offload"
 	depends on TEST
 	help
 	  Enable irq_offload() API which allows functions to be synchronously
@@ -618,7 +618,7 @@ config ARCH_MAPS_ALL_RAM
 	  as reserved) and Z_PAGE_FRAME_MAPPED will not be set.
 
 menuconfig MPU
-	bool "Enable MPU features"
+	bool "MPU features"
 	depends on CPU_HAS_MPU
 	help
 	  This option, when enabled, indicates to the core kernel that an MPU
@@ -699,7 +699,7 @@ config SRAM_REGION_PERMISSIONS
 menu "Floating Point Options"
 
 config FPU
-	bool "Enable floating point unit (FPU)"
+	bool "Floating point unit (FPU)"
 	depends on CPU_HAS_FPU
 	help
 	  This option enables the hardware Floating Point Unit (FPU), in order to
@@ -740,7 +740,7 @@ endmenu
 menu "Cache Options"
 
 config CACHE_MANAGEMENT
-	bool "Enable cache management features"
+	bool "Cache management features"
 	help
 	  This links in the cache management functions (for d-cache and i-cache
 	  where possible).

arch/arc/Kconfig

@@ -168,7 +168,7 @@ config ARC_FIRQ
 	  from the performance point of view.
 
 config ARC_FIRQ_STACK
-	bool "Enable separate firq stack"
+	bool "Separate firq stack"
 	depends on ARC_FIRQ && RGF_NUM_BANKS > 1
 	help
 	  Use separate stack for FIRQ handing. When the fast irq is also a direct
@@ -220,7 +220,7 @@ config ARC_STACK_PROTECTION
 	  prioritized over the MPU-based stack guard.
 
 config ARC_USE_UNALIGNED_MEM_ACCESS
-	bool "Enable unaligned access in HW"
+	bool "Unaligned access in HW"
 	default y if CPU_ARCHS
 	depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS
 	help
@@ -325,7 +325,7 @@ menu "ARC MPU Options"
 depends on CPU_HAS_MPU
 
 config ARC_MPU_ENABLE
-	bool "Enable MPU"
+	bool "MPU"
 	select ARC_MPU
 	help
 	  Enable MPU

arch/arm/core/aarch32/Kconfig

@@ -143,7 +143,7 @@ config RUNTIME_NMI
 	  needed, enable this option and attach it via _NmiHandlerSet().
 
 config PLATFORM_SPECIFIC_INIT
-	bool "Enable platform (SOC) specific startup hook"
+	bool "Platform (SOC) specific startup hook"
 	help
 	  The platform specific initialization code (z_arm_platform_init) is
 	  executed at the beginning of the startup code (__start).

arch/arm/core/aarch32/cortex_m/Kconfig

@@ -280,7 +280,7 @@ config GEN_ISR_TABLES
 	default y
 
 config ZERO_LATENCY_IRQS
-	bool "Enable zero-latency interrupts"
+	bool "Zero-latency interrupts"
 	depends on CPU_CORTEX_M_HAS_BASEPRI
 	help
 	  The kernel may reserve some of the highest interrupts priorities in
@@ -296,7 +296,7 @@ config ZERO_LATENCY_IRQS
 	  kernel functionality.
 
 config DYNAMIC_DIRECT_INTERRUPTS
-	bool "Enable support for dynamic direct interrupts"
+	bool "Support for dynamic direct interrupts"
 	depends on DYNAMIC_INTERRUPTS
 	help
 	  Direct interrupts are designed for performance-critical interrupt
@@ -307,7 +307,7 @@ config DYNAMIC_DIRECT_INTERRUPTS
 	  kernel.
 
 config SW_VECTOR_RELAY
-	bool "Enable Software Vector Relay"
+	bool "Software Vector Relay"
 	help
 	  When building a bootloader firmware this option adds a
 	  vector table relay handler and a vector relay table, to
@@ -316,7 +316,7 @@ config SW_VECTOR_RELAY
 	  with no hardware vector table relocation mechanisms (e.g. VTOR).
 
 config SW_VECTOR_RELAY_CLIENT
-	bool "Enable Software Vector Relay (client)"
+	bool "Software Vector Relay (client)"
 	default y if BOOTLOADER_MCUBOOT && !CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
 	depends on !CPU_CORTEX_M_HAS_VTOR
 	help
@@ -326,7 +326,7 @@ config SW_VECTOR_RELAY_CLIENT
 	  initialization.
 
 config CORTEX_M_DWT
-	bool "Enable and use the DWT"
+	bool "And use the DWT"
 	depends on CPU_CORTEX_M_HAS_DWT
 	default y if TIMING_FUNCTIONS
 	help
@@ -345,7 +345,7 @@ endmenu
 # Trace Unit and the Debug Monitor Exception, or the Memory Protection Unit.
 
 choice NULL_POINTER_EXCEPTION_DETECTION
-	bool "Enable and use null-pointer exception"
+	bool "And use null-pointer exception"
 	# Disable this until https://github.com/zephyrproject-rtos/zephyr/issues/32984 is fixed
 	# default NULL_POINTER_EXCEPTION_DETECTION_DWT if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && CPU_CORTEX_M_HAS_DWT
 	default NULL_POINTER_EXCEPTION_DETECTION_MPU if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && ARM_MPU && !CPU_CORTEX_M_HAS_DWT

arch/riscv/Kconfig

@@ -14,14 +14,14 @@ config COMPRESSED_ISA
 	default y if 64BIT
 
 config FLOAT_HARD
-	bool "Enable hard-float calling convention"
+	bool "Hard-float calling convention"
 	default y
 	depends on FPU
 	help
 	  This option enables the hard-float calling convention.
 
 config RISCV_GP
-	bool "Enable RISC-V global pointer relative addressing"
+	bool "RISC-V global pointer relative addressing"
 	default n
 	help
 	  Use global pointer relative addressing for small globals declared
@@ -50,7 +50,7 @@ config INCLUDE_RESET_VECTOR
 	  prepares for running C code.
 
 config RISCV_SOC_CONTEXT_SAVE
-	bool "Enable SOC-based context saving in IRQ handlers"
+	bool "SOC-based context saving in IRQ handlers"
 	select RISCV_SOC_OFFSETS
 	help
 	  Enable low-level SOC-specific context management, for SOCs
@@ -85,7 +85,7 @@ config RISCV_SOC_CONTEXT_SAVE
 	  pointer address is in a0, and ra contains the return address.
 
 config RISCV_SOC_OFFSETS
-	bool "Enable SOC-based offsets"
+	bool "SOC-based offsets"
 	help
 	  Enabling this option requires that the SoC provide a soc_offsets.h
 	  header which defines the following macros:
@@ -97,7 +97,7 @@ config RISCV_SOC_OFFSETS
 	    See gen_offset.h for more details.
 
 config RISCV_SOC_INTERRUPT_INIT
-	bool "Enable SOC-based interrupt initialization"
+	bool "SOC-based interrupt initialization"
 	help
 	  Enable SOC-based interrupt initialization
 	  (call soc_interrupt_init, within _IntLibInit when enabled)

arch/riscv/core/pmp/Kconfig

@@ -11,7 +11,7 @@ config PMP_SLOT
 	  than the Hardware allow you.
 
 config PMP_POWER_OF_TWO_ALIGNMENT
-	bool "Enable power of two alignment"
+	bool "Power of two alignment"
 	default n
 	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
 	select GEN_PRIV_STACKS

arch/x86/Kconfig

@@ -101,56 +101,56 @@ config X86_CPU_HAS_SSE4A
 if FPU || X86_64
 
 config X86_MMX
-	bool "Enable MMX Support"
+	bool "MMX Support"
 	depends on X86_CPU_HAS_MMX
 	help
 	  This option enables MMX support, and the use of MMX registers
 	  by threads.
 
 config X86_SSE
-	bool "Enable SSE Support"
+	bool "SSE Support"
 	depends on X86_CPU_HAS_SSE
 	help
 	  This option enables SSE support, and the use of SSE registers
 	  by threads.
 
 config X86_SSE2
-	bool "Enable SSE2 Support"
+	bool "SSE2 Support"
 	depends on X86_CPU_HAS_SSE2
 	select X86_SSE
 	help
 	  This option enables SSE2 support.
 
 config X86_SSE3
-	bool "Enable SSE3 Support"
+	bool "SSE3 Support"
 	depends on X86_CPU_HAS_SSE3
 	select X86_SSE
 	help
 	  This option enables SSE3 support.
 
 config X86_SSSE3
-	bool "Enable SSSE3 (Supplemental SSE3) Support"
+	bool "SSSE3 (Supplemental SSE3) Support"
 	depends on X86_CPU_HAS_SSSE3
 	select X86_SSE
 	help
 	  This option enables Supplemental SSE3 support.
 
 config X86_SSE41
-	bool "Enable SSE4.1 Support"
+	bool "SSE4.1 Support"
 	depends on X86_CPU_HAS_SSE41
 	select X86_SSE
 	help
 	  This option enables SSE4.1 support.
 
 config X86_SSE42
-	bool "Enable SSE4.2 Support"
+	bool "SSE4.2 Support"
 	depends on X86_CPU_HAS_SSE42
 	select X86_SSE
 	help
 	  This option enables SSE4.2 support.
 
 config X86_SSE4A
-	bool "Enable SSE4A Support"
+	bool "SSE4A Support"
 	depends on X86_CPU_HAS_SSE4A
 	select X86_SSE
 	help
@@ -336,7 +336,7 @@ config X86_VERY_EARLY_CONSOLE
 	  tree. This mini-driver assumes I/O to the UART is done via ports.
 
 config X86_MMU
-	bool "Enable Memory Management Unit"
+	bool "Memory Management Unit"
 	select MMU
 	help
 	  This options enables the memory management unit present in x86
@@ -450,7 +450,7 @@ config DISABLE_SSBD
 	  require this feature.
 
 config ENABLE_EXTENDED_IBRS
-	bool "Enable Extended IBRS"
+	bool "Extended IBRS"
 	depends on USERSPACE
 	default y if !X86_NO_SPECTRE_V2
 	help
@@ -469,7 +469,7 @@ config X86_BOUNDS_CHECK_BYPASS_MITIGATION
 	  to be immune to it.
 
 config X86_KPTI
-	bool "Enable kernel page table isolation"
+	bool "Kernel page table isolation"
 	default y
 	depends on USERSPACE
 	depends on !X86_NO_MELTDOWN

arch/x86/core/Kconfig.ia32

@@ -6,7 +6,7 @@
 if !X86_64
 
 config NESTED_INTERRUPTS
-	bool "Enable nested interrupts"
+	bool "Nested interrupts"
 	default y
 	help
 	  This option enables support for nested interrupts.

arch/xtensa/Kconfig

@@ -44,7 +44,7 @@ config XTENSA_USE_CORE_CRT1
 	  to false.
 
 config XTENSA_ENABLE_BACKTRACE
-	bool "Enable backtrace on panic exception"
+	bool "Backtrace on panic exception"
 	default y
 	depends on SOC_ESP32
 	help
@@ -56,14 +56,14 @@ config XTENSA_CPU_IDLE_SPIN
 	  Use a spin loop instead of WAITI for the CPU idle state.
 
 config XTENSA_WAITI_BUG
-	bool "Enable workaround sequence for WAITI bug on LX6"
+	bool "Workaround sequence for WAITI bug on LX6"
 	help
 	  SOF traditionally contains this workaround on its ADSP
 	  platforms which prefixes a WAITI entry with 128 NOP
 	  instructions followed by an ISYNC and EXTW.
 
 config XTENSA_SMALL_VECTOR_TABLE_ENTRY
-	bool "Enable workaround for small vector table entries"
+	bool "Workaround for small vector table entries"
 	help
 	  This option enables a small indirection to bypass the size
 	  constraint of the vector table entry and moved the default

boards/arm/adafruit_feather_nrf52840/Kconfig

@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_ENABLE_DCDC
-	bool "Enable DCDC mode"
+	bool "DCDC mode"
 	select SOC_DCDC_NRF52X
 	default y
 	depends on BOARD_ADAFRUIT_FEATHER_NRF52840

boards/arm/bl5340_dvk/Kconfig

@@ -46,17 +46,17 @@ endif # RPMSG_SERVICE_DUAL_IPM_SUPPORT
 if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS
 
 config BOARD_ENABLE_DCDC_APP
-	bool "Enable Application MCU DCDC converter"
+	bool "Application MCU DCDC converter"
 	select SOC_DCDC_NRF53X_APP
 	default y
 
 config BOARD_ENABLE_DCDC_NET
-	bool "Enable Network MCU DCDC converter"
+	bool "Network MCU DCDC converter"
 	select SOC_DCDC_NRF53X_NET
 	default y
 
 config BOARD_ENABLE_DCDC_HV
-	bool "Enable High Voltage DCDC converter"
+	bool "High Voltage DCDC converter"
 	select SOC_DCDC_NRF53X_HV
 	default y
 
@@ -71,7 +71,7 @@ config BT_HCI_VS
 	default y if BT
 
 config BOARD_ENABLE_CPUNET
-	bool "Enable nRF53 Network MCU"
+	bool "NRF53 Network MCU"
 	help
 	  This option enables releasing the Network 'force off' signal, which
 	  as a consequence will power up the Network MCU during system boot.

boards/arm/bl652_dvk/Kconfig

@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_ENABLE_DCDC
-	bool "Enable DCDC mode"
+	bool "DCDC mode"
 	select SOC_DCDC_NRF52X
 	default y
 	depends on BOARD_BL652_DVK