intel_adsp: move cavs to be a series

Intel ADSP CAVS is now a proper series with all CAVS SoCs running under it. This will give us to Intel ADSP series: - CAVS - ACE v1.x Signed-off-by: Anas Nashif <anas.nashif@intel.com>
zephyrproject-rtos · Jul 25, 2022 · 43371d0 · 43371d0
1 parent f91379a
commit 43371d0
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Showing 56 changed files with 136 additions and 199 deletions.
diff --git a/boards/xtensa/intel_adsp_cavs15/Kconfig.board b/boards/xtensa/intel_adsp_cavs15/Kconfig.board
@@ -5,4 +5,4 @@
 
 config  BOARD_INTEL_ADSP_CAVS15
 	bool "Intel ADSP CAVS 1.5"
-	depends on SOC_SERIES_INTEL_CAVS_V15
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
diff --git a/boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15_defconfig b/boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15_defconfig
@@ -2,7 +2,8 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V15=y
+CONFIG_SOC_INTEL_CAVS_V15=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
 CONFIG_BOARD_INTEL_ADSP_CAVS15=y
 
 CONFIG_GEN_ISR_TABLES=y

diff --git a/boards/xtensa/intel_adsp_cavs18/Kconfig.board b/boards/xtensa/intel_adsp_cavs18/Kconfig.board
@@ -5,4 +5,4 @@
 
 config  BOARD_INTEL_ADSP_CAVS18
 	bool "Intel ADSP CAVS 1.8"
-	depends on SOC_SERIES_INTEL_CAVS_V18
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
diff --git a/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig b/boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18_defconfig
@@ -2,8 +2,9 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V18=y
+CONFIG_SOC_INTEL_CAVS_V18=y
 CONFIG_BOARD_INTEL_ADSP_CAVS18=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
 
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n

diff --git a/boards/xtensa/intel_adsp_cavs20/Kconfig.board b/boards/xtensa/intel_adsp_cavs20/Kconfig.board
@@ -5,8 +5,8 @@
 
 config  BOARD_INTEL_ADSP_CAVS20
 	bool "Intel ADSP CAVS 2.0 for Ice Lake"
-	depends on SOC_SERIES_INTEL_CAVS_V20
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
 
 config  BOARD_INTEL_ADSP_CAVS20_JSL
 	bool "Intel ADSP CAVS 2.0 for Jasper Lake"
-	depends on SOC_SERIES_INTEL_CAVS_V20
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
diff --git a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_defconfig
@@ -2,8 +2,9 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V20=y
+CONFIG_SOC_INTEL_CAVS_V20=y
 CONFIG_BOARD_INTEL_ADSP_CAVS20=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
 
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n

diff --git a/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl_defconfig b/boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl_defconfig
@@ -2,8 +2,10 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V20=y
+CONFIG_SOC_INTEL_CAVS_V20=y
 CONFIG_BOARD_INTEL_ADSP_CAVS20_JSL=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
+
 
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n

diff --git a/boards/xtensa/intel_adsp_cavs25/Kconfig.board b/boards/xtensa/intel_adsp_cavs25/Kconfig.board
@@ -5,8 +5,8 @@
 
 config  BOARD_INTEL_ADSP_CAVS25
 	bool "Intel ADSP CAVS 2.5"
-	depends on SOC_SERIES_INTEL_CAVS_V25
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
 
 config  BOARD_INTEL_ADSP_CAVS25_TGPH
 	bool "Intel ADSP CAVS 2.5 for Tiger Lake H PCH"
-	depends on SOC_SERIES_INTEL_CAVS_V25
+	depends on SOC_SERIES_INTEL_ADSP_CAVS
diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig
@@ -2,7 +2,8 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V25=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
+CONFIG_SOC_INTEL_CAVS_V25=y
 CONFIG_BOARD_INTEL_ADSP_CAVS25=y
 
 CONFIG_GEN_ISR_TABLES=y

diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig
@@ -2,8 +2,10 @@
 
 CONFIG_MAIN_STACK_SIZE=2048
 
-CONFIG_SOC_SERIES_INTEL_CAVS_V25=y
+CONFIG_SOC_INTEL_CAVS_V25=y
 CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH=y
+CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y
+
 
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n

diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c
@@ -675,7 +675,7 @@ static int dai_ssp_poll_for_register_delay(uint32_t reg, uint32_t mask,
 
 static inline void dai_ssp_pm_runtime_dis_ssp_clk_gating(struct dai_intel_ssp *dp, uint32_t index)
 {
-#if CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#if CONFIG_SOC_INTEL_CAVS_V15
 	uint32_t shim_reg;
 
 	shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) |
@@ -691,7 +691,7 @@ static inline void dai_ssp_pm_runtime_dis_ssp_clk_gating(struct dai_intel_ssp *d
 
 static inline void dai_ssp_pm_runtime_en_ssp_clk_gating(struct dai_intel_ssp *dp, uint32_t index)
 {
-#if CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#if CONFIG_SOC_INTEL_CAVS_V15
 	uint32_t shim_reg;
 
 	shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) &

diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h
@@ -40,7 +40,7 @@
 #define DAI_INTEL_SSP_PLATFORM_DEFAULT_DELAY	12
 #define DAI_INTEL_SSP_DEFAULT_TRY_TIMES		8
 
-#if CONFIG_SOC_SERIES_INTEL_CAVS_V15
+#if CONFIG_SOC_INTEL_CAVS_V15
 /** \brief Number of 'base' SSP ports available */
 #define DAI_INTEL_SSP_NUM_BASE			4
 /** \brief Number of 'extended' SSP ports available */

diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c
@@ -11,13 +11,13 @@
 #include "intc_cavs.h"
 
 #if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1)
-#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
+#if defined(CONFIG_SOC_INTEL_CAVS_V15)
 #define PER_CPU_OFFSET(x)	(0x40 * x)
-#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V18)
+#elif defined(CONFIG_SOC_INTEL_CAVS_V18)
 #define PER_CPU_OFFSET(x)	(0x40 * x)
-#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V20)
+#elif defined(CONFIG_SOC_INTEL_CAVS_V20)
 #define PER_CPU_OFFSET(x)	(0x40 * x)
-#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V25)
+#elif defined(CONFIG_SOC_INTEL_CAVS_V25)
 #define PER_CPU_OFFSET(x)	(0x40 * x)
 #else
 #error "Must define PER_CPU_OFFSET(x) for SoC"

diff --git a/drivers/ipm/Kconfig b/drivers/ipm/Kconfig
@@ -171,7 +171,7 @@ config IPM_CAVS_HOST_OUTBOX_OFFSET
 config IPM_CAVS_HOST_REGWORD
 	bool "Store first 4 bytes in IPC register"
 	depends on CAVS_IPC
-	depends on !SOC_SERIES_INTEL_CAVS_V15
+	depends on !SOC_INTEL_CAVS_V15
 	help
 	  Protocol variant.  When true, the first four bytes of a
 	  message are passed in the cAVS IDR/TDR register pair instead

diff --git a/drivers/mm/mm_drv_intel_adsp_tlb.c b/drivers/mm/mm_drv_intel_adsp_tlb.c
@@ -45,7 +45,7 @@ DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0));
  * Number of significant bits in the page index (defines the size of
  * the table)
  */
-#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
+#if defined(CONFIG_SOC_INTEL_CAVS_V15)
 # define TLB_PADDR_SIZE 9
 #else
 # define TLB_PADDR_SIZE 11

diff --git a/soc/xtensa/intel_adsp/Kconfig b/soc/xtensa/intel_adsp/Kconfig
@@ -14,6 +14,9 @@ config SOC_FAMILY
 	string
 	default "intel_adsp"
 
+# Select SoC Part No. and configuration options
+source "soc/xtensa/intel_adsp/*/Kconfig.soc"
+
 config CAVS_IPC
 	bool
 	default y if !SOF
@@ -27,11 +30,6 @@ config CAVS_CLOCK
 	  Driver for the CAVS clocks. Allow type of clock (and
 	  thus frequency) to be chosen.
 
-config INTEL_ADSP_CAVS
-	bool
-	help
-	  Indicates a CAVS SoC
-
 config HP_SRAM_RESERVE
 	int "Bytes to reserve at start of HP-SRAM"
 	default 65536
@@ -65,7 +63,6 @@ config ADSP_TRACE_SIMCALL
 	  of an enclosing simulator process.  All window contents will
 	  remain identical.
 
-# Select SoC Part No. and configuration options
-source "soc/xtensa/intel_adsp/*/Kconfig.soc"
+
 
 endif # SOC_FAMILY_INTEL_ADSP
diff --git a/soc/xtensa/intel_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/Kconfig.defconfig
@@ -20,7 +20,7 @@ config DMA_INTEL_ADSP_GPDMA
 	depends on DMA
 
 config XTENSA_CCOUNT_HZ
-	default 400000000 if SOC_SERIES_INTEL_CAVS_V25
+	default 400000000 if SOC_INTEL_CAVS_V25
 	default 200000000
 
 endif # INTEL_ADSP_CAVS
diff --git a/...el_adsp/cavs_v15/Kconfig.defconfig.series → ...ntel_adsp/cavs/Kconfig.defconfig.cavs_v15 b/...el_adsp/cavs_v15/Kconfig.defconfig.series → ...ntel_adsp/cavs/Kconfig.defconfig.cavs_v15
@@ -1,19 +1,18 @@
 # Copyright (c) 2020 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_CAVS_V15
-
-config SOC_SERIES
-	string
-	default "cavs_v15"
+if SOC_INTEL_CAVS_V15
 
 config SOC_TOOLCHAIN_NAME
 	string
 	default "intel_apl_adsp"
 
 config SOC
-	string
-	default "intel_apl_adsp" if SOC_INTEL_CAVS_V15
+	default "intel_apl_adsp"
+
+# For backward compatibility, to be removed
+config SOC_SERIES_INTEL_CAVS_V15
+	def_bool y
 
 config HP_SRAM_RESERVE
 	default 32768
@@ -65,4 +64,4 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-endif # SOC_SERIES_INTEL_CAVS_V15
+endif
diff --git a/...el_adsp/cavs_v18/Kconfig.defconfig.series → ...ntel_adsp/cavs/Kconfig.defconfig.cavs_v18 b/...el_adsp/cavs_v18/Kconfig.defconfig.series → ...ntel_adsp/cavs/Kconfig.defconfig.cavs_v18
@@ -1,22 +1,23 @@
 # Copyright (c) 2020 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_CAVS_V18
+if SOC_INTEL_CAVS_V18
 
-config SOC_SERIES
-	string
-	default "cavs_v18"
 
 config SOC_TOOLCHAIN_NAME
 	string
 	default "intel_s1000"
 
 config SOC
 	string
-	default "intel_cavs_18"
+	default "intel_cnl_adsp"
+
+# For backward compatibility, to be removed
+config SOC_SERIES_INTEL_CAVS_V18
+	def_bool y
 
 config SMP
-       default y
+	default y
 
 # FIXME: these DSPs can have more cores, but Zephyr only supports up to 2 cores on them
 config MP_NUM_CPUS
@@ -57,4 +58,4 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-endif
+endif # SOC_INTEL_CAVS_V18
diff --git a/...el_adsp/cavs_v20/Kconfig.defconfig.series → ...ntel_adsp/cavs/Kconfig.defconfig.cavs_v20 b/...el_adsp/cavs_v20/Kconfig.defconfig.series → ...ntel_adsp/cavs/Kconfig.defconfig.cavs_v20
@@ -1,22 +1,22 @@
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020,2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_CAVS_V20
-
-config SOC_SERIES
-	string
-	default "cavs_v20"
+if SOC_INTEL_CAVS_V20
 
 config SOC_TOOLCHAIN_NAME
 	string
 	default "intel_s1000"
 
 config SOC
 	string
-	default "intel_cavs_20"
+	default "intel_icl_adsp"
+
+# For backward compatibility, to be removed
+config SOC_SERIES_INTEL_CAVS_V20
+	def_bool y
 
 config SMP
-       default y
+	default y
 
 # FIXME: these DSPs can have more cores, but Zephyr only supports up to 2 cores on them
 config MP_NUM_CPUS
@@ -57,4 +57,4 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-endif # SOC_SERIES_INTEL_CAVS_V20
+endif # SOC_INTEL_CAVS_V20
diff --git a/...el_adsp/cavs_v25/Kconfig.defconfig.series → ...ntel_adsp/cavs/Kconfig.defconfig.cavs_v25 b/...el_adsp/cavs_v25/Kconfig.defconfig.series → ...ntel_adsp/cavs/Kconfig.defconfig.cavs_v25
@@ -1,26 +1,25 @@
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020,2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_INTEL_CAVS_V25
-
-config SOC_SERIES
-	string
-	default "cavs_v25"
+if SOC_INTEL_CAVS_V25
 
 config SOC_TOOLCHAIN_NAME
 	string
 	default "intel_s1000"
 
 config SOC
-	string
-	default "intel_cavs_25"
+	default "intel_tgl_adsp"
+
+# For backward compatibility, to be removed
+config SOC_SERIES_INTEL_CAVS_V25
+	def_bool y
 
 # Hardware has four cores, limited to two pending test fixes
 config MP_NUM_CPUS
 	default 2
 
 config SMP
-       default y
+	default y
 
 config XTENSA_TIMER
 	default n
@@ -88,4 +87,4 @@ config KERNEL_VM_SIZE
 
 endif
 
-endif # SOC_SERIES_INTEL_CAVS_V25
+endif # SOC_INTEL_CAVS_V25
diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_INTEL_ADSP_CAVS
+
+config SOC_SERIES
+	string
+	default "cavs"
+
+config INTEL_ADSP_CAVS
+	def_bool y
+
+source "soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs*"
+
+endif # SOC_SERIES_INTEL_ADSP_CAVS
diff --git a/...xtensa/intel_adsp/cavs_v15/Kconfig.series → soc/xtensa/intel_adsp/cavs/Kconfig.series b/...xtensa/intel_adsp/cavs_v15/Kconfig.series → soc/xtensa/intel_adsp/cavs/Kconfig.series
@@ -1,15 +1,14 @@
-# Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2017,2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_INTEL_CAVS_V15
-	bool "Intel CAVS v1.5"
+config SOC_SERIES_INTEL_ADSP_CAVS
+	bool "Intel CAVS"
 	select SOC_FAMILY_INTEL_ADSP
 	select XTENSA
-	select INTEL_ADSP_CAVS
 	select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
 	select XTENSA_RESET_VECTOR
 	select XTENSA_USE_CORE_CRT1
 	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
 	select ARCH_HAS_COHERENCE
 	help
-	  Intel CAVS v1.5
+	  Intel ADSP CAVS