soc: arm: Introduce Infineon CAT1/PSoC 6 SOC integration

Add initial version of Infineon CAT1/PSoC 6 SOC integration. Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
zephyrproject-rtos · Feb 2, 2022 · 38b7f55 · 38b7f55
1 parent 87a40b2
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diff --git a/soc/arm/infineon_cat1/CMakeLists.txt b/soc/arm/infineon_cat1/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
diff --git a/soc/arm/infineon_cat1/Kconfig b/soc/arm/infineon_cat1/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+
+config SOC_FAMILY_CAT1
+    bool
+
+config SOC_FAMILY_CAT1A
+    bool
+
+if SOC_FAMILY_CAT1
+source "soc/arm/infineon_cat1/*/Kconfig.soc"
+
+config SOC_FAMILY
+    string
+    default "infineon_cat1"
+
+endif # SOC_FAMILY_CAT1
diff --git a/soc/arm/infineon_cat1/Kconfig.defconfig b/soc/arm/infineon_cat1/Kconfig.defconfig
@@ -0,0 +1,4 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/infineon_cat1/*/Kconfig.defconfig"
diff --git a/soc/arm/infineon_cat1/Kconfig.soc b/soc/arm/infineon_cat1/Kconfig.soc
@@ -0,0 +1,4 @@
+# Copyright (c) 2021, Cypress
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/infineon_cat1/*/Kconfig.series"
diff --git a/soc/arm/infineon_cat1/psoc6/CMakeLists.psoc6_01.txt b/soc/arm/infineon_cat1/psoc6/CMakeLists.psoc6_01.txt
@@ -0,0 +1,63 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+# add MPN defines
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6036BZI_F04 CY8C6036BZI_F04)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6016BZI_F04 CY8C6016BZI_F04)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6116BZI_F54 CY8C6116BZI_F54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6136BZI_F14 CY8C6136BZI_F14)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6136BZI_F34 CY8C6136BZI_F34)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6137BZI_F14 CY8C6137BZI_F14)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6137BZI_F34 CY8C6137BZI_F34)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6137BZI_F54 CY8C6137BZI_F54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6117BZI_F34 CY8C6117BZI_F34)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6246BZI_D04 CY8C6246BZI_D04)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247BZI_D44 CY8C6247BZI_D44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247BZI_D34 CY8C6247BZI_D34)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247BZI_D54 CY8C6247BZI_D54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6336BZI_BLF03 CY8C6336BZI_BLF03)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6316BZI_BLF03 CY8C6316BZI_BLF03)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6316BZI_BLF53 CY8C6316BZI_BLF53)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6336BZI_BLD13 CY8C6336BZI_BLD13)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BLD43 CY8C6347BZI_BLD43)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BLD33 CY8C6347BZI_BLD33)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BLD53 CY8C6347BZI_BLD53)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347FMI_BLD13 CY8C6347FMI_BLD13)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347FMI_BLD43 CY8C6347FMI_BLD43)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347FMI_BLD33 CY8C6347FMI_BLD33)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347FMI_BLD53 CY8C6347FMI_BLD53)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6137FDI_F02 CY8C6137FDI_F02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6117FDI_F02 CY8C6117FDI_F02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247FDI_D02 CY8C6247FDI_D02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247FDI_D32 CY8C6247FDI_D32)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6336BZI_BUD13 CY8C6336BZI_BUD13)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BUD43 CY8C6347BZI_BUD43)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BUD33 CY8C6347BZI_BUD33)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BUD53 CY8C6347BZI_BUD53)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6337BZI_BLF13 CY8C6337BZI_BLF13)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6136FDI_F42 CY8C6136FDI_F42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247FDI_D52 CY8C6247FDI_D52)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6136FTI_F42 CY8C6136FTI_F42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247FTI_D52 CY8C6247FTI_D52)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247BZI_AUD54 CY8C6247BZI_AUD54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6336BZI_BLF04 CY8C6336BZI_BLF04)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6316BZI_BLF04 CY8C6316BZI_BLF04)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6316BZI_BLF54 CY8C6316BZI_BLF54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6336BZI_BLD14 CY8C6336BZI_BLD14)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BLD44 CY8C6347BZI_BLD44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BLD34 CY8C6347BZI_BLD34)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347BZI_BLD54 CY8C6347BZI_BLD54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247BFI_D54 CY8C6247BFI_D54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CYBLE_416045_02 CYBLE_416045_02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347FMI_BUD53 CY8C6347FMI_BUD53)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347FMI_BUD13 CY8C6347FMI_BUD13)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347FMI_BUD43 CY8C6347FMI_BUD43)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347FMI_BUD33 CY8C6347FMI_BUD33)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6137WI_F54 CY8C6137WI_F54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6117WI_F34 CY8C6117WI_F34)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6247WI_D54 CY8C6247WI_D54)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6336LQI_BLF02 CY8C6336LQI_BLF02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6336LQI_BLF42 CY8C6336LQI_BLF42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6347LQI_BLD52 CY8C6347LQI_BLD52)
diff --git a/soc/arm/infineon_cat1/psoc6/CMakeLists.psoc6_02.txt b/soc/arm/infineon_cat1/psoc6/CMakeLists.psoc6_02.txt
@@ -0,0 +1,38 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+# add MPN defines
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CYB0644ABZI_S2D44 CYB0644ABZI_S2D44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CYS0644ABZI_S2D44 CYS0644ABZI_S2D44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624ABZI_S2D44A0 CY8C624ABZI_S2D44A0)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624ABZI_S2D44 CY8C624ABZI_S2D44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624AAZI_S2D44 CY8C624AAZI_S2D44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624AFNI_S2D43 CY8C624AFNI_S2D43)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624ABZI_S2D04 CY8C624ABZI_S2D04)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624ABZI_S2D14 CY8C624ABZI_S2D14)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624AAZI_S2D14 CY8C624AAZI_S2D14)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6248AZI_S2D14 CY8C6248AZI_S2D14)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6248BZI_S2D44 CY8C6248BZI_S2D44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6248AZI_S2D44 CY8C6248AZI_S2D44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6248FNI_S2D43 CY8C6248FNI_S2D43)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614ABZI_S2F04 CY8C614ABZI_S2F04)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614AAZI_S2F04 CY8C614AAZI_S2F04)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614AFNI_S2F03 CY8C614AFNI_S2F03)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614AAZI_S2F14 CY8C614AAZI_S2F14)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614ABZI_S2F44 CY8C614ABZI_S2F44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614AAZI_S2F44 CY8C614AAZI_S2F44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614AFNI_S2F43 CY8C614AFNI_S2F43)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6148BZI_S2F44 CY8C6148BZI_S2F44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6148AZI_S2F44 CY8C6148AZI_S2F44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6148FNI_S2F43 CY8C6148FNI_S2F43)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624ABZI_D44 CY8C624ABZI_D44)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624ALQI_S2D42 CY8C624ALQI_S2D42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C624ALQI_S2D02 CY8C624ALQI_S2D02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6248LQI_S2D42 CY8C6248LQI_S2D42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6248LQI_S2D02 CY8C6248LQI_S2D02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614ALQI_S2F42 CY8C614ALQI_S2F42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C614ALQI_S2F02 CY8C614ALQI_S2F02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6148LQI_S2F42 CY8C6148LQI_S2F42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6148LQI_S2F02 CY8C6148LQI_S2F02)
diff --git a/soc/arm/infineon_cat1/psoc6/CMakeLists.psoc6_03.txt b/soc/arm/infineon_cat1/psoc6/CMakeLists.psoc6_03.txt
@@ -0,0 +1,33 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+# add MPN defines
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245AZI_S3D72 CY8C6245AZI_S3D72)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245LQI_S3D72 CY8C6245LQI_S3D72)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245FNI_S3D71 CY8C6245FNI_S3D71)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245AZI_S3D62 CY8C6245AZI_S3D62)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245LQI_S3D62 CY8C6245LQI_S3D62)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245AZI_S3D42 CY8C6245AZI_S3D42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245LQI_S3D42 CY8C6245LQI_S3D42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CYB06445LQI_S3D42 CYB06445LQI_S3D42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245FNI_S3D41 CY8C6245FNI_S3D41)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245AZI_S3D12 CY8C6245AZI_S3D12)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245LQI_S3D12 CY8C6245LQI_S3D12)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245FNI_S3D11 CY8C6245FNI_S3D11)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245AZI_S3D02 CY8C6245AZI_S3D02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6245LQI_S3D02 CY8C6245LQI_S3D02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145AZI_S3F72 CY8C6145AZI_S3F72)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145LQI_S3F72 CY8C6145LQI_S3F72)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145FNI_S3F71 CY8C6145FNI_S3F71)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145AZI_S3F62 CY8C6145AZI_S3F62)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145LQI_S3F62 CY8C6145LQI_S3F62)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145AZI_S3F42 CY8C6145AZI_S3F42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145LQI_S3F42 CY8C6145LQI_S3F42)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145FNI_S3F41 CY8C6145FNI_S3F41)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145AZI_S3F12 CY8C6145AZI_S3F12)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145LQI_S3F12 CY8C6145LQI_S3F12)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145FNI_S3F11 CY8C6145FNI_S3F11)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145AZI_S3F02 CY8C6145AZI_S3F02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6145LQI_S3F02 CY8C6145LQI_S3F02)
diff --git a/soc/arm/infineon_cat1/psoc6/CMakeLists.psoc6_04.txt b/soc/arm/infineon_cat1/psoc6/CMakeLists.psoc6_04.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+# add MPN defines
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244AZI_S4D92 CY8C6244AZI_S4D92)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244LQI_S4D92 CY8C6244LQI_S4D92)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244AZI_S4D93 CY8C6244AZI_S4D93)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244AZI_S4D82 CY8C6244AZI_S4D82)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244LQI_S4D82 CY8C6244LQI_S4D82)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244AZI_S4D83 CY8C6244AZI_S4D83)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244AZI_S4D62 CY8C6244AZI_S4D62)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244LQI_S4D62 CY8C6244LQI_S4D62)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244AZI_S4D12 CY8C6244AZI_S4D12)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6244LQI_S4D12 CY8C6244LQI_S4D12)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144AZI_S4F92 CY8C6144AZI_S4F92)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144LQI_S4F92 CY8C6144LQI_S4F92)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144AZI_S4F93 CY8C6144AZI_S4F93)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144AZI_S4F82 CY8C6144AZI_S4F82)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144LQI_S4F82 CY8C6144LQI_S4F82)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144AZI_S4F83 CY8C6144AZI_S4F83)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144AZI_S4F62 CY8C6144AZI_S4F62)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144LQI_S4F62 CY8C6144LQI_S4F62)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144AZI_S4F12 CY8C6144AZI_S4F12)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CY8C6144LQI_S4F12 CY8C6144LQI_S4F12)
diff --git a/soc/arm/infineon_cat1/psoc6/CMakeLists.txt b/soc/arm/infineon_cat1/psoc6/CMakeLists.txt
@@ -0,0 +1,23 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+zephyr_include_directories(.)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.psoc6_01.txt)
+include(${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.psoc6_02.txt)
+include(${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.psoc6_03.txt)
+include(${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.psoc6_04.txt)
+
+# PSoC 6 family defines
+zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_CAT1A COMPONENT_CAT1A)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_CAT1 COMPONENT_CAT1)
+
+# Add sections
+zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_CAT1 NOINIT noinit.ld)
+
+# Add section for cm0p image ROM
+zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_CAT1A ROM_START SORT_KEY 0 rom_cm0image.ld)
+
+# Add section for cm0p image RAM
+zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_CAT1A RAM_SECTIONS SORT_KEY 0 ram_cm0image.ld)
diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig
@@ -0,0 +1,21 @@
+# Infineon PSoC 6 MCU line
+
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_CAT1
+source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*"
+
+config SOC_SERIES
+    default "psoc6"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+    default 100000000
+
+config ROM_START_OFFSET
+    default 0x2000  if SOC_PSOC6_CM0P_SLEEP
+
+config SRAM_OFFSET
+    default 0x2000 if SOC_PSOC6_CM0P_SLEEP
+
+endif # SOC_FAMILY_CAT1A
diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc
@@ -0,0 +1,4 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*"
diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_01 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_01
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6_01 based MCU default configuration
+
+if SOC_DIE_PSOC6_01
+
+config NUM_IRQS
+    default  32 if CPU_CORTEX_M0PLUS
+    default 147 if CPU_CORTEX_M4
+
+# add additional die specific params
+
+endif # SOC_DIE_PSOC6_01
diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6_02 based MCU default configuration
+
+if SOC_DIE_PSOC6_02
+
+config NUM_IRQS
+    default  32 if CPU_CORTEX_M0PLUS
+    default 168 if CPU_CORTEX_M4
+
+# add additional die specific params
+
+endif # SOC_DIE_PSOC6_02
diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_03 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_03
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6_03 based MCU default configuration
+
+if SOC_DIE_PSOC6_03
+
+config NUM_IRQS
+    default  32 if CPU_CORTEX_M0PLUS
+    default 138 if CPU_CORTEX_M4
+
+# add additional die specific params
+
+endif # SOC_DIE_PSOC6_03
diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6_04 based MCU default configuration
+
+if SOC_DIE_PSOC6_04
+
+config NUM_IRQS
+    default  32 if CPU_CORTEX_M0PLUS
+    default 141 if CPU_CORTEX_M4
+
+# add additional die specific params
+
+endif # SOC_DIE_PSOC6_04
diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.series b/soc/arm/infineon_cat1/psoc6/Kconfig.series
@@ -0,0 +1,34 @@
+# Copyright (c) 2021 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+# Cypress PSoC™ 6 MCU lines
+config SOC_SERIES_PSOC_60
+    bool "Infineon PSoC™ 60 series MCU(Value Line)"
+    select SOC_FAMILY_CAT1
+    help
+      Enable support for Infineon PSoC™ 60 MCU series
+
+config SOC_SERIES_PSOC_61
+    bool "Infineon PSoC™ 61 series MCU (Programmable Line)"
+    select SOC_FAMILY_CAT1
+    help
+      Enable support for Infineon PSoC™ 61 MCU series
+
+config SOC_SERIES_PSOC_62
+    bool "Infineon PSoC™ 62 series MCU (Performance Line)"
+    select SOC_FAMILY_CAT1
+    help
+      Enable support for Infineon PSoC™ 62 MCU series
+
+config SOC_SERIES_PSOC_63
+    bool "Infineon PSoC™ 63 series MCU (Connectivity Line)"
+    select SOC_FAMILY_CAT1
+    help
+      Enable support for Infineon PSoC™ 63 MCU series
+
+config SOC_SERIES_PSOC_64
+    bool "Infineon PSoC™ 64 series MCU (Security Line)"
+    select SOC_FAMILY_CAT1
+    help
+      Enable support for Infineon PSoC™ 64 MCU series
+