drivers: Modification of IFX ADC driver to function with new platform

	- Modification of IFX drivers for ADC functionality of new
	  platform cyw920829m2evk_02
	- Addition of configuration files to relevant sample/test for
	  cyw920829m2evk_02

Signed-off-by: McAtee Maxwell (CSS ICW SW MTO INT 2) <Maxwell.McAtee@infineon.com>

boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml

@@ -17,6 +17,7 @@ supported:
   - uart
   - clock_control
   - bluetooth
+  - adc
   - watchdog
   - spi
   - i2c

drivers/adc/adc_ifx_cat1.c

@@ -22,7 +22,9 @@
 LOG_MODULE_REGISTER(ifx_cat1_adc, CONFIG_ADC_LOG_LEVEL);
 
 #if defined(PASS_SARMUX_PADS0_PORT)
-	#define _ADCSAR_PORT PASS_SARMUX_PADS0_PORT
+	#define _ADC_PORT PASS_SARMUX_PADS0_PORT
+#elif defined(ADCMIC_GPIO_ADC_IN0_PORT)
+	#define _ADC_PORT ADCMIC_GPIO_ADC_IN0_PORT
 #else
 	#error The selected device does not supported ADC
 #endif
@@ -33,15 +35,24 @@ LOG_MODULE_REGISTER(ifx_cat1_adc, CONFIG_ADC_LOG_LEVEL);
 #define ADC_CAT1_RESOLUTION             (12u)
 #define ADC_CAT1_REF_INTERNAL_MV        (1200u)
 
+#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
+#define IFX_ADC_NUM_CHANNELS sizeof(cyhal_pin_map_adcmic_gpio_adc_in) / sizeof(cyhal_pin_map_adcmic_gpio_adc_in[0])
+#else
+#define IFX_ADC_NUM_CHANNELS CY_SAR_SEQ_NUM_CHANNELS
+#endif
+
 struct ifx_cat1_adc_data {
 	struct adc_context ctx;
 	const struct device *dev;
 	cyhal_adc_t adc_obj;
-	cyhal_adc_channel_t adc_chan_obj[CY_SAR_SEQ_NUM_CHANNELS];
+	cyhal_adc_channel_t adc_chan_obj[IFX_ADC_NUM_CHANNELS];
 	uint16_t *buffer;
 	uint16_t *repeat_buffer;
 	uint32_t channels;
 	uint32_t channels_mask;
+	#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B
+	struct k_work adc_worker_thread;
+	#endif
 };
 
 struct ifx_cat1_adc_config {
@@ -74,13 +85,42 @@ static void _cyhal_adc_event_callback(void *callback_arg, cyhal_adc_event_t even
 	LOG_DBG("%s ISR triggered.", dev->name);
 }
 
+#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B
+static void ifx_cat1_adc_worker(struct k_work *adc_worker_thread)
+{
+	struct ifx_cat1_adc_data *data = CONTAINER_OF(adc_worker_thread,
+				struct ifx_cat1_adc_data, adc_worker_thread);
+
+	uint32_t channels = data->channels;
+	int32_t result;
+	uint32_t channel_id;
+
+	while (channels != 0) {
+		channel_id = find_lsb_set(channels) - 1;
+		channels &= ~BIT(channel_id);
+
+		result = cyhal_adc_read(&data->adc_chan_obj[channel_id]);
+		/* Legacy API for BWC. Convert from signed to unsigned by adding 0x800 to
+		 * convert the lowest signed 12-bit number to 0x0.
+		 */
+		*data->buffer = (uint16_t)(result + 0x800);
+		data->buffer++;
+	}
+	adc_context_on_sampling_done(&data->ctx, data->dev);
+}
+#endif
+
 static void adc_context_start_sampling(struct adc_context *ctx)
 {
 	struct ifx_cat1_adc_data *data = CONTAINER_OF(ctx, struct ifx_cat1_adc_data, ctx);
 
 	data->repeat_buffer = data->buffer;
 
+	#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
+	k_work_submit(&data->adc_worker_thread);
+	#else
 	Cy_SAR_StartConvert(data->adc_obj.base, CY_SAR_START_CONVERT_SINGLE_SHOT);
+	#endif
 }
 
 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
@@ -99,9 +139,9 @@ static int ifx_cat1_adc_channel_setup(const struct device *dev,
 	struct ifx_cat1_adc_data *data = dev->data;
 	cy_rslt_t result;
 
-	cyhal_gpio_t vplus = CYHAL_GET_GPIO(_ADCSAR_PORT, channel_cfg->input_positive);
+	cyhal_gpio_t vplus = CYHAL_GET_GPIO(_ADC_PORT, channel_cfg->input_positive);
 	cyhal_gpio_t vminus = channel_cfg->differential ?
-			      CYHAL_GET_GPIO(_ADCSAR_PORT, channel_cfg->input_negative) :
+			      CYHAL_GET_GPIO(_ADC_PORT, channel_cfg->input_negative) :
 			      CYHAL_ADC_VNEG;
 	uint32_t acquisition_ns = ADC_CAT1_DEFAULT_ACQUISITION_NS;
 
@@ -158,7 +198,7 @@ static int validate_buffer_size(const struct adc_sequence *sequence)
 	int active_channels = 0;
 	int total_buffer_size;
 
-	for (int i = 0; i < CY_SAR_SEQ_NUM_CHANNELS; i++) {
+	for (int i = 0; i < IFX_ADC_NUM_CHANNELS; i++) {
 		if (sequence->channels & BIT(i)) {
 			active_channels++;
 		}
@@ -250,7 +290,7 @@ static int ifx_cat1_adc_init(const struct device *dev)
 	data->dev = dev;
 
 	/* Initialize ADC. The ADC block which can connect to the input pin is selected */
-	result = cyhal_adc_init(&data->adc_obj, CYHAL_GET_GPIO(_ADCSAR_PORT, 0), NULL);
+	result = cyhal_adc_init(&data->adc_obj, CYHAL_GET_GPIO(_ADC_PORT, 0), NULL);
 	if (result != CY_RSLT_SUCCESS) {
 		LOG_ERR("ADC initialization failed. Error: 0x%08X\n", (unsigned int)result);
 		return -EIO;
@@ -275,12 +315,20 @@ static const struct adc_driver_api adc_cat1_driver_api = {
 	.ref_internal = ADC_CAT1_REF_INTERNAL_MV
 };
 
+#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B
+#define ADC_WORKER_THREAD_INIT() \
+	.adc_worker_thread = Z_WORK_INITIALIZER(ifx_cat1_adc_worker),
+#else
+#define ADC_WORKER_THREAD_INIT()
+#endif
+
 /* Macros for ADC instance declaration */
 #define INFINEON_CAT1_ADC_INIT(n)					       \
 	static struct ifx_cat1_adc_data ifx_cat1_adc_data##n = {	       \
 		ADC_CONTEXT_INIT_TIMER(ifx_cat1_adc_data##n, ctx),	       \
 		ADC_CONTEXT_INIT_LOCK(ifx_cat1_adc_data##n, ctx),	       \
 		ADC_CONTEXT_INIT_SYNC(ifx_cat1_adc_data##n, ctx),	       \
+		ADC_WORKER_THREAD_INIT() \
 	};								       \
 									       \
 	static const struct ifx_cat1_adc_config adc_cat1_cfg_##n = {	       \

drivers/clock_control/clock_control_ifx_cat1.c

@@ -533,9 +533,16 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
 	clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf3));
 	clock_div = DT_PROP(DT_NODELABEL(clk_hf3), clock_div);
 
+	#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) && \
+		defined(CONFIG_USE_INFINEON_ADC)
+	Cy_SysClk_ClkHfSetSource(3, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+	Cy_SysClk_ClkHfSetDivider(3, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+	Cy_SysClk_ClkHfEnable(3);
+	#else
 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[3], clock_div)) {
 		return -EIO;
 	}
+	#endif
 #endif
 
 	/* Configure the HF[4] to source defined in tree device 'clk_hf4' node */

dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi

@@ -98,6 +98,14 @@
 			#gpio-cells = <2>;
 		};
 
+		adc0: adc@40520000 {
+			compatible = "infineon,cat1-adc";
+			reg = <0x40520000 0x10000>;
+			interrupts = <67 6>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
 		ipc0: ipc@401d0000 {
 			compatible = "infineon,cat1-ipc";
 			reg = <0x401d0000 0x10000>;

modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt

@@ -73,7 +73,6 @@ zephyr_library_sources_ifdef(CONFIG_SOC_DIE_PSOC6_04
   ${hal_cat1a_dir}/source/triggers/cyhal_triggers_psoc6_04.c)
 
 # High level interface for interacting with CAT1 hardware
-zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC     ${hal_dir}/source/cyhal_adc_sar.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_FLASH   ${hal_dir}/source/cyhal_nvm.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C     ${hal_dir}/source/cyhal_i2c.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${hal_dir}/source/cyhal_lptimer.c)
@@ -86,6 +85,12 @@ zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TRNG    ${hal_dir}/source/cyhal
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART    ${hal_dir}/source/cyhal_uart.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_WDT     ${hal_dir}/source/cyhal_wdt.c)
 
+if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
+  zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC     ${hal_dir}/source/cyhal_adc_mic.c)
+else()
+  zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC     ${hal_dir}/source/cyhal_adc_sar.c)
+endif()
+
 if(CONFIG_USE_INFINEON_ADC)
   zephyr_library_sources(${hal_dir}/source/cyhal_analog_common.c)
   zephyr_library_sources(${hal_dir}/source/cyhal_dma.c)

modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt

@@ -43,6 +43,14 @@ zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART     ${pdl_drv_dir}/source/
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_FLASH    ${pdl_drv_dir}/source/cy_flash.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_WDT      ${pdl_drv_dir}/source/cy_wdt.c)
 
+zephyr_library_sources(${pdl_drv_dir}/source/cy_tcpwm_pwm.c)
+
+if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
+  zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC      ${pdl_drv_dir}/source/cy_adcmic.c)
+else()
+  zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC      ${pdl_drv_dir}/source/cy_sar.c)
+endif()
+
 if(CONFIG_USE_INFINEON_TRNG)
   zephyr_library_sources(${pdl_drv_dir}/source/cy_crypto.c)
   zephyr_library_sources(${pdl_drv_dir}/source/cy_crypto_core_trng_v1.c)

samples/drivers/adc/adc_dt/boards/cyw920829m2evk_02.overlay

@@ -0,0 +1,56 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@4 {
+		reg = <4>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <4>;   /* P3.4 */
+	};
+
+	channel@5 {
+		reg = <5>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <5>;   /* P3.5 */
+	};
+
+	channel@6 {
+		reg = <6>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <6>;   /* P3.6 */
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <7>;   /* P3.7 */
+	};
+};

tests/drivers/adc/adc_api/boards/cyw920829m2evk_02.conf

@@ -0,0 +1 @@
+CONFIG_TEST_USERSPACE=n

tests/drivers/adc/adc_api/boards/cyw920829m2evk_02.overlay

@@ -0,0 +1,38 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 4>, <&adc0 5>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@4 {
+		reg = <4>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <4>;   /* P3.4 */
+	};
+
+	channel@5 {
+		reg = <5>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <5>;   /* P3.5 */
+	};
+};