soc: ti_k3: Add TI J721E SoC R5

Add minimal SoC support for the TI J721E SoC series Cortex-R5 core.

Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>

dts/arm/ti/j721e-pinctrl.dtsi

@@ -0,0 +1,25 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
+
+&pinctrl {
+	uart0_tx_default: uart0_tx_default {
+		pinmux = <0x1e8 (PIN_OUTPUT | 0)>;
+	};
+
+	uart0_rx_default: uart0_rx_default {
+		pinmux = <0x1ec (PIN_INPUT | 0)>;
+	};
+
+	uart2_tx_default: uart2_tx_default {
+		pinmux = <0x1c (PIN_OUTPUT | 14)>;
+	};
+
+	uart2_rx_default: uart2_rx_default {
+		pinmux = <0x14 (PIN_INPUT | 14)>;
+	};
+};

dts/arm/ti/j721e.dtsi

@@ -7,14 +7,20 @@
 #include <mem.h>
 #include <freq.h>
 #include <arm/armv7-r.dtsi>
-/ {
 
+/ {
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	uart0: uart@2800000 {
+	pinctrl: pinctrl@11c000 {
+		compatible = "ti,k3-pinctrl";
+		reg = <0x0011c000 0x2b4>;
+		status = "okay";
+	};
+
+	uart2: uart@2820000 {
 		compatible = "ns16550";
-		reg = <0x02800000 0x100>;
+		reg = <0x02820000 0x100>;
 		clock-frequency = <48000000>;
 		current-speed = <115200>;
 		reg-shift = <2>;

soc/arm/ti_k3/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+add_subdirectory(${SOC_SERIES})

soc/arm/ti_k3/Kconfig

@@ -0,0 +1,16 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_TI_K3
+	bool
+
+if SOC_FAMILY_TI_K3
+config SOC_FAMILY
+	string
+	default "ti_k3"
+
+source "soc/arm/ti_k3/*/Kconfig.soc"
+
+endif # SOC_FAMILY_TI_k3

soc/arm/ti_k3/Kconfig.defconfig

@@ -0,0 +1,10 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_TI_K3
+
+source "soc/arm/ti_k3/*/Kconfig.defconfig.series"
+
+endif # SOC_FAMILY_TI_K3

soc/arm/ti_k3/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/ti_k3/*/Kconfig.series"

soc/arm/ti_k3/j721e/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(soc.c)

soc/arm/ti_k3/j721e/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_TI_J721E_R5
+
+config SOC
+	default "j721e_r5"
+
+endif

soc/arm/ti_k3/j721e/Kconfig.defconfig.j721e_r5

@@ -0,0 +1,8 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC
+	default "j721e_r5"
+	depends on SOC_TI_J721E_R5

soc/arm/ti_k3/j721e/Kconfig.defconfig.series

@@ -0,0 +1,36 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_TI_J721E
+
+source "soc/arm/ti_k3/j721e/Kconfig.defconfig.j721e*"
+
+config SOC_SERIES
+	default "j721e"
+
+config NUM_IRQS
+	default 512
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 10000
+
+config UART_NS16550
+	default y
+
+choice UART_NS16550_VARIANT
+	default UART_NS16550_VARIANT_NS16750
+endchoice
+
+config PINCTRL
+	default y
+
+# This is required for the entry point address for the elf to be zero
+config KERNEL_ENTRY
+	default "_vector_table"
+
+endif # SOC_SERIES_TI_J721E

soc/arm/ti_k3/j721e/Kconfig.series

@@ -0,0 +1,13 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_TI_J721E
+	bool "TI Jacinto J721E SoC series"
+	select ARM
+	select SOC_FAMILY_TI_K3
+	select CPU_CORTEX_R5
+	select ARM_CUSTOM_INTERRUPT_CONTROLLER
+	help
+	  Enable support for the TI Jacinto J721E SoC series

soc/arm/ti_k3/j721e/Kconfig.soc

@@ -0,0 +1,13 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "TI J721E SoC Selection"
+	depends on SOC_SERIES_TI_J721E
+
+config SOC_TI_J721E_R5
+	bool "TI J721E R5"
+
+endchoice

soc/arm/ti_k3/j721e/ipc_rpmsg_linux_resource_table.h

@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef IPC_RPMSG_LINUX_RESOURCE_TABLE_H_
+#define IPC_RPMSG_LINUX_RESOURCE_TABLE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stddef.h>
+#include <zephyr/sys/util_macro.h>
+
+/*
+ * Keep structure and defines in the file in sync with the linux kernel
+ */
+
+/** \brief Virtio type for Remote Proc Messaging
+ */
+#define RPMESSAGE_RSC_VIRTIO_ID_RPMSG  (7U)
+
+/**
+ * \name Resource Entry type
+ *
+ * @{
+ */
+
+/** \brief trace type */
+#define RPMESSAGE_RSC_TYPE_TRACE       (2U)
+/** \brief VDEV type */
+#define RPMESSAGE_RSC_TYPE_VDEV        (3U)
+
+/**@}*/
+
+/** \brief Macro to specify VRING memory needs to be dynamically allocated by linux */
+#define RPMESSAGE_RSC_VRING_ADDR_ANY (0xFFFFFFFFU)
+
+/** \brief Macro to specify linux trace version */
+#define RPMESSAGE_RSC_TRACE_INTS_VER0        (0 << 16)
+/** \brief Macro to specify linux trace version */
+#define RPMESSAGE_RSC_TRACE_INTS_VER1        BIT(16)
+/** \brief Max length of trace name */
+#define RPMESSAGE_RSC_TRACE_NAME_LEN         (32u)
+
+/**
+ * \brief Resource Table Header
+ */
+struct rpmessage_rschdr {
+	uint32_t ver;
+	/**< Version Number, set to 1 */
+	uint32_t num;
+	/**< Number of Entries, MUST be 2 */
+	uint32_t reserved[2];
+	/**< Reserved for future use, set to 0 */
+};
+
+/**
+ * \brief Structure used for remoteproc trace
+ */
+struct rpmessage_rsctrace {
+	uint32_t  type;
+	/** Type of trace, MUST be set to TYPE_TRACE | TRACE_INTS_VER0 */
+	uint32_t  da;
+	/**< Device Address, physical address of location of trace buffer in remote side */
+	uint32_t  len;
+	/**< Length of trace buffer  */
+	uint32_t  reserved;
+	/**< Reserved for future use, set to 0  */
+	uint8_t   name[RPMESSAGE_RSC_TRACE_NAME_LEN];
+	/**<  Name of the trace */
+};
+
+/**
+ * \brief Resource Table Device VRing Structure
+ */
+struct rpmessage_rscvring {
+	uint32_t  da;
+	/**< device address, physical address of VRING,
+	 *   set to RPMSG_VRING_ADDR_ANY, updated by linux, with actual address
+	 */
+	uint32_t  align;
+	/**< Alignment used between AVAIL and USED structures, updated by linux */
+	uint32_t  num;
+	/**< Number of message buffers, MUST be 256 */
+	uint32_t  notifyid;
+	/**< NotifyId for receive channel, set 1 for TX VRING and 2 for RX VRING */
+	uint32_t  reserved;
+	/**< Reserved for future use, set to 0 */
+};
+
+/**
+ *  \brief VDEV structure
+ */
+struct rpmessage_rscvdev {
+	uint32_t  type;
+	/**< type of VDEV, set to TYPE_VDEV */
+	uint32_t  id;
+	/**< ID of VDEV, set to VIRTIO_ID_RPMSG */
+	uint32_t  notifyid;
+	/**< Not used, set to 0  */
+	uint32_t  dfeatures;
+	/**< Not used, set to 1 */
+	uint32_t  gfeatures;
+	/**< not used, set to 0 */
+	uint32_t  config_len;
+	/**< not used, set to 0 */
+	uint8_t   status;
+	/**< updated by linux, after linux init, this should be 0x7 */
+	uint8_t   num_of_vrings;
+	/**< number of vrings, set to 2 */
+	uint8_t   reserved[2];
+	/**< Reserved for future use, set to 0 */
+};
+
+/**
+ *  \brief IPC Resource Table used by IPC app
+ */
+struct rpmessage_resourcetable {
+	struct rpmessage_rschdr base;
+	/**< Header Information */
+	uint32_t offset[2];
+	/**< offset to VDEV and TRACE entries */
+	struct rpmessage_rscvdev vdev;
+	/**< VDEV entry */
+	struct rpmessage_rscvring  vring0;
+	/**< TX VRING  */
+	struct rpmessage_rscvring  vring1;
+	/**< RX VRING */
+	struct rpmessage_rsctrace trace;
+	/**< Trace entry  */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IPC_RPMSG_LINUX_RESOURCE_TABLE_H_ */

soc/arm/ti_k3/j721e/linker.ld

@@ -0,0 +1,20 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_a_r/scripts/linker.ld>
+
+SECTIONS
+{
+    SECTION_PROLOGUE(.resource_table,,)
+    {
+        KEEP(*(.resource_table*))
+    } > RAM
+
+    .log_shared_mem :
+    {
+        *(.log_shared_mem*)
+    } > RAM
+}