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drivers: ethernet: Add Xilinx AXI Enet driver
The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs. This patch adds a driver and device tree bindings for the Ethernet MAC core and its MDIO controller. The driver was tested on a RISC-V softcore in an FPGA design, with an RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree bindings match the device tree generated by Vitis hsi. Note that Vitis generates one of the two included compatible strings depending on version. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
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# | ||
#Xilinx AXI 1G / 2.5G Ethernet Subsystem | ||
# | ||
#Copyright(c) 2024, CISPA Helmholtz Center for Information Security | ||
#SPDX-License-Identifier: Apache-2.0 | ||
# | ||
|
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config ETH_XILINX_AXIENET | ||
bool "Xilinx AXI Ethernet Driver" | ||
default y | ||
depends on DT_HAS_XLNX_AXI_ETHERNET_7_2_ENABLED || DT_HAS_XLNX_AXI_ETHERNET_1_00_A_ENABLED | ||
depends on DT_HAS_XLNX_ETH_DMA_ENABLED && DMA_XILINX_AXI_DMA | ||
help | ||
Enable Xilinx 1G / 2.5G AXI Ethernet driver, | ||
commonly found on FPGAs. |
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