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gd32e50x: patch HAL
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Patch GD32E50X HAL according to the requirements listed in the
repository README.md file.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
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@gmarull @nandojve
gmarull authored and nandojve committed Aug 11, 2022
1 parent b24036a commit b0cf0eb
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Showing 8 changed files with 25 additions and 25 deletions.
2 changes: 2 additions & 0 deletions gd32e50x/cmsis/gd/gd32e50x/include/gd32e50x.h
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Expand Up @@ -470,7 +470,9 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#ifndef BIT
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
#endif
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))

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6 changes: 0 additions & 6 deletions gd32e50x/cmsis/gd/gd32e50x/source/system_gd32e50x.c
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Expand Up @@ -136,12 +136,6 @@ void SystemInit (void)

/* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
system_clock_config();

#ifdef VECT_TAB_SRAM
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
#else
nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
#endif
}

/*!
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6 changes: 3 additions & 3 deletions gd32e50x/standard_peripheral/include/gd32e50x_can.h
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Expand Up @@ -781,9 +781,9 @@ typedef enum
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */

/* CAN working mode */
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
#define GD32_CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
#define GD32_CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
#define GD32_CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */

/* filter bits */
#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
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6 changes: 6 additions & 0 deletions gd32e50x/standard_peripheral/include/gd32e50x_i2c.h
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Expand Up @@ -561,6 +561,12 @@ typedef enum
#define BUSTOA_DETECT_SCL_LOW ((uint32_t)0x00000000U) /*!< BUSTOA is used to detect SCL low timeout */
#define BUSTOA_DETECT_IDLE I2C2_TIMEOUT_TOIDLE /*!< BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle */

/* I2C clock frequency, MHz */
#define I2CCLK_MAX ((uint32_t)0x0000007FU) /*!< i2cclk maximum value */
#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */
#define I2CCLK_FM_MIN ((uint32_t)0x00000008U) /*!< i2cclk minimum value for fast mode */
#define I2CCLK_FM_PLUS_MIN ((uint32_t)0x00000018U) /*!< i2cclk minimum value for fast mode plus */

/* function declarations */
/* functions of I2C0~2 */
/* reset I2C */
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2 changes: 1 addition & 1 deletion gd32e50x/standard_peripheral/include/gd32e50x_timer.h
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Expand Up @@ -600,7 +600,7 @@ void timer_deinit(uint32_t timer_periph);
/* initialize TIMER init parameter struct */
void timer_struct_para_init(timer_parameter_struct* initpara);
/* initialize TIMER counter */
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
/* enable a TIMER */
void timer_enable(uint32_t timer_periph);
/* disable a TIMER */
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24 changes: 12 additions & 12 deletions gd32e50x/standard_peripheral/source/gd32e50x_can.c
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Expand Up @@ -736,7 +736,7 @@ ErrStatus can_frequency_set(uint32_t can_periph, uint32_t hz)
uint32_t fdctl_status;
/* The maximum baud rate support to 1M */
if(hz <= 1000000U) {
if(SUCCESS == can_working_mode_set(can_periph, CAN_MODE_INITIALIZE)){
if(SUCCESS == can_working_mode_set(can_periph, GD32_CAN_MODE_INITIALIZE)){
reg_temp = CAN_BT(can_periph);
reg_temp &= (CAN_BT_LCMOD | CAN_BT_SCMOD);
fdctl_status = CAN_FDCTL(can_periph);
Expand All @@ -755,7 +755,7 @@ ErrStatus can_frequency_set(uint32_t can_periph, uint32_t hz)
reval = ERROR;
}

if(SUCCESS != can_working_mode_set(can_periph, CAN_MODE_NORMAL)){
if(SUCCESS != can_working_mode_set(can_periph, GD32_CAN_MODE_NORMAL)){
reval = ERROR;
}
}else{
Expand All @@ -777,13 +777,13 @@ ErrStatus can_fd_frequency_set(uint32_t can_periph, uint32_t hz)
{
ErrStatus reval = SUCCESS;

if(SUCCESS == can_working_mode_set(can_periph, CAN_MODE_INITIALIZE)){
if(SUCCESS == can_working_mode_set(can_periph, GD32_CAN_MODE_INITIALIZE)){
CAN_DBT(can_periph) = dev_can_fd_baudrate_set(hz);
}else {
reval = ERROR;
}

if(SUCCESS != can_working_mode_set(can_periph, CAN_MODE_NORMAL)){
if(SUCCESS != can_working_mode_set(can_periph, GD32_CAN_MODE_NORMAL)){
reval = ERROR;
}

Expand Down Expand Up @@ -829,7 +829,7 @@ ErrStatus can_frequency_set(uint32_t can_periph, uint32_t hz)

/* The maximum baud rate support to 1M */
if(hz <= 1000000U) {
if(SUCCESS == can_working_mode_set(can_periph, CAN_MODE_INITIALIZE)){
if(SUCCESS == can_working_mode_set(can_periph, GD32_CAN_MODE_INITIALIZE)){
reg_temp = CAN_BT(can_periph);
reg_temp &= (CAN_BT_LCMOD | CAN_BT_SCMOD);

Expand All @@ -838,7 +838,7 @@ ErrStatus can_frequency_set(uint32_t can_periph, uint32_t hz)
reval = ERROR;
}

if(SUCCESS != can_working_mode_set(can_periph, CAN_MODE_NORMAL)){
if(SUCCESS != can_working_mode_set(can_periph, GD32_CAN_MODE_NORMAL)){
reval = ERROR;
}
}else{
Expand Down Expand Up @@ -1376,9 +1376,9 @@ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
\arg CANx(x=0,1,2),the CAN2 only for GD32E50X_CL and GD32E508
\param[in] can_working_mode
only one parameter can be selected which is shown as below:
\arg CAN_MODE_INITIALIZE
\arg CAN_MODE_NORMAL
\arg CAN_MODE_SLEEP
\arg GD32_CAN_MODE_INITIALIZE
\arg GD32_CAN_MODE_NORMAL
\arg GD32_CAN_MODE_SLEEP
\param[out] none
\retval ErrStatus: SUCCESS or ERROR
*/
Expand All @@ -1388,7 +1388,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
/* timeout for IWS or also for SLPWS bits */
uint32_t timeout = CAN_TIMEOUT;

if(CAN_MODE_INITIALIZE == working_mode){
if(GD32_CAN_MODE_INITIALIZE == working_mode){
/* disable sleep mode */
CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
/* set initialize mode */
Expand All @@ -1402,7 +1402,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
}else{
flag = SUCCESS;
}
}else if(CAN_MODE_NORMAL == working_mode){
}else if(GD32_CAN_MODE_NORMAL == working_mode){
/* enter normal mode */
CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
/* wait the acknowledge */
Expand All @@ -1414,7 +1414,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
}else{
flag = SUCCESS;
}
}else if(CAN_MODE_SLEEP == working_mode){
}else if(GD32_CAN_MODE_SLEEP == working_mode){
/* disable initialize mode */
CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
/* set sleep mode */
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2 changes: 0 additions & 2 deletions gd32e50x/standard_peripheral/source/gd32e50x_i2c.c
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Expand Up @@ -39,8 +39,6 @@ OF SUCH DAMAGE.
#define I2C_ERROR_HANDLE(s) do{}while(1)

/* I2C register bit mask */
#define I2CCLK_MAX ((uint32_t)0x0000007FU) /*!< i2cclk maximum value */
#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */
#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */
#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */
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2 changes: 1 addition & 1 deletion gd32e50x/standard_peripheral/source/gd32e50x_timer.c
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Expand Up @@ -157,7 +157,7 @@ void timer_struct_para_init(timer_parameter_struct* initpara)
\param[out] none
\retval none
*/
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
{
/* configure the counter prescaler value */
TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
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