riscv: add new rv32emc configurations
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gcc/config/riscv/t-zephyr
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| march=rv32emc_zicsr/mabi=ilp32e \ | ||
| march=rv32emc_zicsr_zba_zbb_zbc_zbs/mabi=ilp32e \ | ||
| march=rv32emc_zicsr_zicntr_zba_zbb_zbc_zbs/mabi=ilp32e \ | ||
| march=rv32emc_zicsr_zicntr_zba_zbb_zbc_zbs_zcb/mabi=ilp32e \ |
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Here you are adding rv32emc multi-lib variants without Zifencei (i.e. support for IFENCE.I) -- is this intentional?
I am asking because IFENCE.I used to be part of the mandatory base instruction set, and generally speaking, it is hard to imagine a processor implementation without one.
Note that there already exist rv32emc_zicsr_zifencei variants if you are targeting processors with Zifencei support.
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Yes, adding variants without Zifencei is the main purpose of this PR.
I'm also adding variants with zcb and zicntr as those extensions were not used in Zephyr SDK yet, so calling this change "add rv32emc configurations without Zifencei" would not convey full scope here, that's why I picked such generic commit title.
Those variants are not supported yet in GCC version used in SDK. I'll change commit title.
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sdk-ng PR: zephyrproject-rtos/sdk-ng#744 |
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Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Update test case for armv8.1-m.main that supports conditional
arithmetic.
armv7-m:
push {r4, lr}
ldr r4, .L6
ldr r4, [r4]
lsls r4, r4, #29
it mi
addmi r2, r2, #1
bl bar
movs r0, #0
pop {r4, pc}
armv8.1-m.main:
push {r3, r4, r5, lr}
ldr r4, .L5
ldr r5, [r4]
tst r5, #4
csinc r2, r2, r2, eq
bl bar
movs r0, #0
pop {r3, r4, r5, pc}
gcc/testsuite/ChangeLog:
* gcc.target/arm/epilog-1.c: Use check-function-bodies.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit ec86e87)
Namely:
rv32emc_zicsrrv32emc_zicsr_zba_zbb_zbc_zbsrv32emc_zicsr_zicntr_zba_zbb_zbc_zbsrv32emc_zicsr_zicntr_zba_zbb_zbc_zbs_zcb