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zeeshanrafique23 Public
My GitHub Profile README. Don't just fork, star it, so others can find it too! 👀
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aws-fpga Public
Forked from aws/aws-fpgaOfficial repository of the AWS EC2 FPGA Hardware and Software Development Kit
VHDL Other UpdatedNov 24, 2024 -
mdu Public
M-extension for RISC-V cores.
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TENNA Public
Forked from deepware-ai/TENNATENNA: Tiny Embedded Neural Network Accelerator
MIT License UpdatedJan 16, 2023 -
cocotb Public
Forked from cocotb/cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Python BSD 3-Clause "New" or "Revised" License UpdatedNov 27, 2022 -
RV32I-Logisim Public
RV32I single cycle simulation on open-source software Logisim.
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ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog Apache License 2.0 UpdatedOct 1, 2021 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedOct 1, 2021 -
rv-compressed Public
Compressed instruction decoder (C-extension) for RISC-V Cores.
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serv Public
Forked from olofk/servSERV - The SErial RISC-V CPU
Verilog ISC License UpdatedSep 20, 2021 -
fpnew Public
Forked from openhwgroup/cvfpuParametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
SystemVerilog Other UpdatedSep 3, 2021 -
azadi Public
Forked from merledu/azadiDeprecated: Azadi is an SoC with 32 bit RISC-V CPU core.
SystemVerilog UpdatedAug 26, 2021 -
corescore Public
Forked from olofk/corescoreCoreScore
Verilog Apache License 2.0 UpdatedAug 21, 2021 -
open_mpw_precheck Public
Forked from efabless/mpw_precheckPython Apache License 2.0 UpdatedAug 10, 2021 -
tcl Public
This repo contains the basic programs and practice code for tcl beginners.
1 UpdatedDec 24, 2020 -
Buraq-mini-sv Public
Forked from merledu/Buraq-miniThis repository is the contain systemverilog version of Buraq-mini with a seperate branch for veriloator team.
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Buraq-mini Public
RISC-V 5-stage 32-bit (RV32IM) processor.
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RV32I-Chisel Public
This repo contains the files of the RV32I Single-cycle processor in CHISEL.