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MIPS: Lantiq: Add initial support for Lantiq SoCs
Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. [Ralf: Remove some cargo cult programming and fixed formatting.] Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2252/ Patchwork: https://patchwork.linux-mips.org/patch/2371/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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/* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms of the GNU General Public License version 2 as published | ||
* by the Free Software Foundation. | ||
* | ||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org> | ||
*/ | ||
#ifndef _LANTIQ_H__ | ||
#define _LANTIQ_H__ | ||
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#include <linux/irq.h> | ||
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/* generic reg access functions */ | ||
#define ltq_r32(reg) __raw_readl(reg) | ||
#define ltq_w32(val, reg) __raw_writel(val, reg) | ||
#define ltq_w32_mask(clear, set, reg) \ | ||
ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg) | ||
#define ltq_r8(reg) __raw_readb(reg) | ||
#define ltq_w8(val, reg) __raw_writeb(val, reg) | ||
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/* register access macros for EBU and CGU */ | ||
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) | ||
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) | ||
#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) | ||
#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) | ||
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extern __iomem void *ltq_ebu_membase; | ||
extern __iomem void *ltq_cgu_membase; | ||
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extern unsigned int ltq_get_cpu_ver(void); | ||
extern unsigned int ltq_get_soc_type(void); | ||
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/* clock speeds */ | ||
#define CLOCK_60M 60000000 | ||
#define CLOCK_83M 83333333 | ||
#define CLOCK_111M 111111111 | ||
#define CLOCK_133M 133333333 | ||
#define CLOCK_167M 166666667 | ||
#define CLOCK_200M 200000000 | ||
#define CLOCK_266M 266666666 | ||
#define CLOCK_333M 333333333 | ||
#define CLOCK_400M 400000000 | ||
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/* spinlock all ebu i/o */ | ||
extern spinlock_t ebu_lock; | ||
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/* some irq helpers */ | ||
extern void ltq_disable_irq(struct irq_data *data); | ||
extern void ltq_mask_and_ack_irq(struct irq_data *data); | ||
extern void ltq_enable_irq(struct irq_data *data); | ||
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/* find out what caused the last cpu reset */ | ||
extern int ltq_reset_cause(void); | ||
#define LTQ_RST_CAUSE_WDTRST 0x20 | ||
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#define IOPORT_RESOURCE_START 0x10000000 | ||
#define IOPORT_RESOURCE_END 0xffffffff | ||
#define IOMEM_RESOURCE_START 0x10000000 | ||
#define IOMEM_RESOURCE_END 0xffffffff | ||
#define LTQ_FLASH_START 0x10000000 | ||
#define LTQ_FLASH_MAX 0x04000000 | ||
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#endif |
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/* | ||
* This file is subject to the terms and conditions of the GNU General Public | ||
* License. See the file "COPYING" in the main directory of this archive | ||
* for more details. | ||
* | ||
*/ | ||
#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H | ||
#define __ASM_MIPS_MACH_LANTIQ_WAR_H | ||
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#define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
#define R4600_V1_HIT_CACHEOP_WAR 0 | ||
#define R4600_V2_HIT_CACHEOP_WAR 0 | ||
#define R5432_CP0_INTERRUPT_WAR 0 | ||
#define BCM1250_M3_WAR 0 | ||
#define SIBYTE_1956_WAR 0 | ||
#define MIPS4K_ICACHE_REFILL_WAR 0 | ||
#define MIPS_CACHE_SYNC_WAR 0 | ||
#define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
#define RM9000_CDEX_SMP_WAR 0 | ||
#define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
#define R10000_LLSC_WAR 0 | ||
#define MIPS34K_MISSED_ITLB_WAR 0 | ||
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#endif |
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# Copyright (C) 2010 John Crispin <blogic@openwrt.org> | ||
# | ||
# This program is free software; you can redistribute it and/or modify it | ||
# under the terms of the GNU General Public License version 2 as published | ||
# by the Free Software Foundation. | ||
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obj-y := irq.o setup.o clk.o prom.o | ||
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
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# | ||
# Lantiq | ||
# | ||
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platform-$(CONFIG_LANTIQ) += lantiq/ | ||
cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq | ||
load-$(CONFIG_LANTIQ) = 0xffffffff80002000 |
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/* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms of the GNU General Public License version 2 as published | ||
* by the Free Software Foundation. | ||
* | ||
* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> | ||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org> | ||
*/ | ||
#include <linux/io.h> | ||
#include <linux/module.h> | ||
#include <linux/init.h> | ||
#include <linux/kernel.h> | ||
#include <linux/types.h> | ||
#include <linux/clk.h> | ||
#include <linux/err.h> | ||
#include <linux/list.h> | ||
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#include <asm/time.h> | ||
#include <asm/irq.h> | ||
#include <asm/div64.h> | ||
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#include <lantiq_soc.h> | ||
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#include "clk.h" | ||
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struct clk { | ||
const char *name; | ||
unsigned long rate; | ||
unsigned long (*get_rate) (void); | ||
}; | ||
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static struct clk *cpu_clk; | ||
static int cpu_clk_cnt; | ||
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/* lantiq socs have 3 static clocks */ | ||
static struct clk cpu_clk_generic[] = { | ||
{ | ||
.name = "cpu", | ||
.get_rate = ltq_get_cpu_hz, | ||
}, { | ||
.name = "fpi", | ||
.get_rate = ltq_get_fpi_hz, | ||
}, { | ||
.name = "io", | ||
.get_rate = ltq_get_io_region_clock, | ||
}, | ||
}; | ||
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static struct resource ltq_cgu_resource = { | ||
.name = "cgu", | ||
.start = LTQ_CGU_BASE_ADDR, | ||
.end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1, | ||
.flags = IORESOURCE_MEM, | ||
}; | ||
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/* remapped clock register range */ | ||
void __iomem *ltq_cgu_membase; | ||
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void clk_init(void) | ||
{ | ||
cpu_clk = cpu_clk_generic; | ||
cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic); | ||
} | ||
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static inline int clk_good(struct clk *clk) | ||
{ | ||
return clk && !IS_ERR(clk); | ||
} | ||
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unsigned long clk_get_rate(struct clk *clk) | ||
{ | ||
if (unlikely(!clk_good(clk))) | ||
return 0; | ||
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if (clk->rate != 0) | ||
return clk->rate; | ||
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if (clk->get_rate != NULL) | ||
return clk->get_rate(); | ||
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return 0; | ||
} | ||
EXPORT_SYMBOL(clk_get_rate); | ||
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struct clk *clk_get(struct device *dev, const char *id) | ||
{ | ||
int i; | ||
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for (i = 0; i < cpu_clk_cnt; i++) | ||
if (!strcmp(id, cpu_clk[i].name)) | ||
return &cpu_clk[i]; | ||
BUG(); | ||
return ERR_PTR(-ENOENT); | ||
} | ||
EXPORT_SYMBOL(clk_get); | ||
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void clk_put(struct clk *clk) | ||
{ | ||
/* not used */ | ||
} | ||
EXPORT_SYMBOL(clk_put); | ||
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static inline u32 ltq_get_counter_resolution(void) | ||
{ | ||
u32 res; | ||
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__asm__ __volatile__( | ||
".set push\n" | ||
".set mips32r2\n" | ||
"rdhwr %0, $3\n" | ||
".set pop\n" | ||
: "=&r" (res) | ||
: /* no input */ | ||
: "memory"); | ||
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return res; | ||
} | ||
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void __init plat_time_init(void) | ||
{ | ||
struct clk *clk; | ||
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if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) | ||
panic("Failed to insert cgu memory\n"); | ||
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if (request_mem_region(ltq_cgu_resource.start, | ||
resource_size(<q_cgu_resource), "cgu") < 0) | ||
panic("Failed to request cgu memory\n"); | ||
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ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, | ||
resource_size(<q_cgu_resource)); | ||
if (!ltq_cgu_membase) { | ||
pr_err("Failed to remap cgu memory\n"); | ||
unreachable(); | ||
} | ||
clk = clk_get(0, "cpu"); | ||
mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); | ||
write_c0_compare(read_c0_count()); | ||
clk_put(clk); | ||
} |
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/* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms of the GNU General Public License version 2 as published | ||
* by the Free Software Foundation. | ||
* | ||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org> | ||
*/ | ||
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#ifndef _LTQ_CLK_H__ | ||
#define _LTQ_CLK_H__ | ||
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extern void clk_init(void); | ||
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extern unsigned long ltq_get_cpu_hz(void); | ||
extern unsigned long ltq_get_fpi_hz(void); | ||
extern unsigned long ltq_get_io_region_clock(void); | ||
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#endif |
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/* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms of the GNU General Public License version 2 as published | ||
* by the Free Software Foundation. | ||
* | ||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org> | ||
*/ | ||
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#include <linux/init.h> | ||
#include <linux/cpu.h> | ||
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#include <lantiq.h> | ||
#include <lantiq_soc.h> | ||
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/* no ioremap possible at this early stage, lets use KSEG1 instead */ | ||
#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) | ||
#define ASC_BUF 1024 | ||
#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) | ||
#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) | ||
#define TXMASK 0x3F00 | ||
#define TXOFFSET 8 | ||
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void prom_putchar(char c) | ||
{ | ||
unsigned long flags; | ||
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local_irq_save(flags); | ||
do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); | ||
if (c == '\n') | ||
ltq_w32('\r', LTQ_ASC_TBUF); | ||
ltq_w32(c, LTQ_ASC_TBUF); | ||
local_irq_restore(flags); | ||
} |
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