Universal Asynchronous Receiver and Transmitter

A fully-featured, Verilator-compatible UART (Universal Asynchronous Receiver/Transmitter) implementation in SystemVerilog with a comprehensive C++ testbench.

Transmitter

• 10-bit shift register (start + 8 data + stop)
• Busy flag prevents overwriting during transmission
• Least significant bit ("LSB")-first transmission
• Automatic frame generation

Receiver

• Four-state FSM: IDLE → START → DATA → STOP
• Start bit validation to prevent false triggers
• Stop bit checking for frame error detection
• Ready pulse signals completed byte reception
• LSB-first reception with proper bit alignment

Getting Started

Prerequisites

• Verilator (version 4.0 or later)
• C++ compiler (g++, clang++)
• Make
• Homebrew

Installation

sh setup.sh make

Testbench

The included testbench (sim_main.cpp).

Test Cases

1. Reset Test: Verifies proper initialization
2. Single Byte Transmission: Tests TX path with 0x55
3. Single Byte Reception: Tests RX path with 0xAA
4. Loopback Test: Multiple bytes (0x00, 0xFF, 0x42, 0xA5, 0x5A)

License

MIT

References

• UART Protocol Specification
• Verilator Documentation