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Re-coded Xilinx primitives for Verilator use

Verilog 45 5 Updated Mar 1, 2024

simple web ui to manage mcp (model context protocol) servers in the claude app

TypeScript 187 28 Updated Dec 21, 2024

Through DPI-C, part of the SVUVM API is encapsulated into a Python API, so that Python can be used to write testcases to avoid frequent compilation

C 3 Updated Apr 7, 2025

DOULOS Easier UVM Code Generator

Perl 32 17 Updated May 6, 2017

Contains the code examples from The UVM Primer Book sorted by chapters.

SystemVerilog 525 212 Updated Dec 24, 2021

EasierUVM from Doulos now written in Python for easier UVM with framework and template generator

Python 11 6 Updated Sep 28, 2022

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Python 210 28 Updated Nov 23, 2024

Simple template-based UVM code generator

SystemVerilog 25 5 Updated Jan 4, 2023

I2C models for cocotb

Python 33 13 Updated Mar 19, 2025

CORE-V MCU UVM Environment and Test Bench

SystemVerilog 21 8 Updated Jul 19, 2024

AMBA AXI VIP

SystemVerilog 394 110 Updated Jun 28, 2024
SystemVerilog 8 3 Updated Feb 13, 2025
SystemVerilog 92 20 Updated Sep 20, 2023

oreboot is a fork of coreboot, with C removed, written in Rust.

Rust 1,658 108 Updated Apr 12, 2025

muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.

C++ 76 10 Updated Mar 6, 2025

CMSIS-NN Library

C 264 71 Updated Feb 18, 2025

This is MCP server for Claude that gives it terminal control, file system search and diff file editing capabilities

TypeScript 1,724 178 Updated Apr 15, 2025

A generic framework for on-demand, incrementalized computation. Inspired by adapton, glimmer, and rustc's query system.

Rust 2,292 170 Updated Apr 10, 2025

Train your AI self, amplify you, bridge the world

Python 10,723 736 Updated Apr 16, 2025

Simple UVM environment for experimenting with Verilator.

SystemVerilog 20 3 Updated Jan 1, 2025

Cadence is a distributed, scalable, durable, and highly available orchestration engine to execute asynchronous long-running business logic in a scalable and resilient way.

Go 8,594 822 Updated Apr 16, 2025

SystemVerilog RTL and UVM RAL model generators for RgGen

Ruby 14 1 Updated Feb 19, 2025

Connecting SystemC with SystemVerilog

C++ 40 18 Updated Mar 25, 2012

SystemVerilog FSM generator

Python 30 8 Updated May 5, 2024

A Hardware Description Language based on the Rust Programming Language

Rust 200 12 Updated Apr 8, 2025

SOLID for Raspberry Pi 4

35 3 Updated May 20, 2024

signal query language

JavaScript 6 1 Updated Dec 20, 2024

VSCode plugin for VCDrom integration

JavaScript 10 2 Updated Nov 14, 2024

A Python library that generates static type annotations by collecting runtime types

Python 4,875 178 Updated Jul 15, 2024

A simple Rust like Result type for Python 3. Fully type annotated.

Python 45 Updated Jan 8, 2025
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