uvm AXI BFM(bus functional model)

Must-have verilog systemverilog modules

UVM APB VIP, part of AMBA3&AMBA4 feature supported

an open source uvm verification platform for e200 (riscv)

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

An UVM example of UART

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

AMBA AXI VIP