microblaze: Add definitions for FSR reg fields

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
yakuizhao · Sep 9, 2010 · bdc0bf2 · bdc0bf2
1 parent 8b33d9e
commit bdc0bf2
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
@@ -91,6 +91,13 @@ struct CPUMBState;
 #define          ESR_EC_DATA_TLB        10
 #define          ESR_EC_INSN_TLB        11
 
+/* Floating Point Status Register (FSR) Bits */
+#define FSR_IO          (1<<4) /* Invalid operation */
+#define FSR_DZ          (1<<3) /* Divide-by-zero */
+#define FSR_OF          (1<<2) /* Overflow */
+#define FSR_UF          (1<<1) /* Underflow */
+#define FSR_DO          (1<<0) /* Denormalized operand error */
+
 /* Version reg.  */
 /* Basic PVR mask */
 #define PVR0_PVR_FULL_MASK              0x80000000