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libcontainer: cgroups: add intel_rdt support in runc
This PR fixes issue opencontainers#433 opencontainers#433 About Intel RDT/CAT feature: Intel platforms with new Xeon CPU support Resource Director Technology (RDT). Intel Cache Allocation Technology (CAT) is a sub-feature of RDT. Currently L3 Cache is the only resource that is supported in RDT. This feature provides a way for the software to restrict cache allocation to a defined 'subset' of L3 cache which may be overlapping with other 'subsets'. The different subsets are identified by class of service (CLOS) and each CLOS has a capacity bitmask (CBM). More information can be found in the section 17.16 of Intel Software Developer Manual. About intel_rdt cgroup: Linux kernel 4.6 (or later) will introduce new cgroup subsystem 'intel_rdt' with kernel config CONFIG_INTEL_RDT. The 'intel_rdt' cgroup manages L3 cache allocation. It has a file 'l3_cbm' which represents the L3 cache capacity bitmask (CBM). The CBM needs to have only *contiguous bits set* and number of bits that can be set is less than the max bits. The max bits in the CBM is varied among supported Intel platforms. The tasks belonging to a cgroup get to fill in the L3 cache represented by the CBM. For example, if the max bits in the CBM is 10 and the L3 cache size is 10MB, each bit represents 1MB of the L3 cache capacity. Root cgroup always has all the bits set in the l3_cbm. User can create more cgroups with mkdir syscall. By default the child cgroups inherit the CBM from parent. User can change the CBM specified in hex for each cgroup. For more information about intel_rdt cgroup: https://lkml.org/lkml/2015/12/17/574 An example: Root cgroup: intel_rdt.l3_cbm == 0xfffff, the max bits of CBM is 20 L3 cache size: 55 MB This assigns 11 MB (1/5) of L3 cache to the child group: $ /bin/echo 0xf > intel_rdt.l3_cbm Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,75 @@ | ||
// +build linux | ||
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package fs | ||
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import ( | ||
"fmt" | ||
"strconv" | ||
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"github.com/opencontainers/runc/libcontainer/cgroups" | ||
"github.com/opencontainers/runc/libcontainer/configs" | ||
) | ||
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type IntelRdtGroup struct { | ||
} | ||
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func (s *IntelRdtGroup) Name() string { | ||
return "intel_rdt" | ||
} | ||
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func (s *IntelRdtGroup) Apply(d *cgroupData) error { | ||
dir, err := d.join("intel_rdt") | ||
if err != nil { | ||
if !cgroups.IsNotFound(err) { | ||
return err | ||
} | ||
// We will not return err here when: | ||
// 1. The h/w platform doesn't support Intel RDT/CAT feature, | ||
// intel_rdt cgroup is not enabled in kernel. | ||
// 2. intel_rdt cgroup is not mounted | ||
return nil | ||
} | ||
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if err := s.Set(dir, d.config); err != nil { | ||
return err | ||
} | ||
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return nil | ||
} | ||
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func (s *IntelRdtGroup) Set(path string, cgroup *configs.Cgroup) error { | ||
// The valid CBM (capacity bitmask) is a *contiguous bits set* and | ||
// number of bits that can be set is less than the max bit. The max | ||
// bits in the CBM is varied among supported Intel platforms. | ||
// | ||
// By default the child cgroups inherit the CBM from parent. The CBM | ||
// in a child cgroup should be a subset of the CBM in parent. Kernel | ||
// will check if it is valid when writing. | ||
// | ||
// e.g., 0xfffff in root cgroup indicates the max bits of CBM is 20 | ||
// bits, which mapping to entire L3 cache capacity. Some valid CBM | ||
// values to Set in children cgroup: 0xf, 0xf0, 0x3ff, 0x1f00 and etc. | ||
if cgroup.Resources.IntelRdtL3Cbm != 0 { | ||
l3CbmStr := fmt.Sprintf("0x%s", strconv.FormatUint(cgroup.Resources.IntelRdtL3Cbm, 16)) | ||
if err := writeFile(path, "intel_rdt.l3_cbm", l3CbmStr); err != nil { | ||
return err | ||
} | ||
} | ||
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return nil | ||
} | ||
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func (s *IntelRdtGroup) Remove(d *cgroupData) error { | ||
return removePath(d.path("intel_rdt")) | ||
} | ||
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func (s *IntelRdtGroup) GetStats(path string, stats *cgroups.Stats) error { | ||
value, err := getCgroupParamUintHex(path, "intel_rdt.l3_cbm") | ||
if err != nil { | ||
return fmt.Errorf("failed to parse intel_rdt.l3_cbm - %s", err) | ||
} | ||
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stats.IntelRdtStats.L3Cbm = value | ||
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return nil | ||
} |
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Original file line number | Diff line number | Diff line change |
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// +build linux | ||
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package fs | ||
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import ( | ||
"strconv" | ||
"testing" | ||
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"github.com/opencontainers/runc/libcontainer/cgroups" | ||
) | ||
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func TestIntelRdtSetL3Cbm(t *testing.T) { | ||
helper := NewCgroupTestUtil("intel_rdt", t) | ||
defer helper.cleanup() | ||
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const ( | ||
l3CbmBefore = 0xf | ||
l3CbmAfter = 0xf0 | ||
) | ||
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helper.writeFileContents(map[string]string{ | ||
"intel_rdt.l3_cbm": strconv.FormatUint(l3CbmBefore, 16), | ||
}) | ||
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helper.CgroupData.config.Resources.IntelRdtL3Cbm = l3CbmAfter | ||
intelrdt := &IntelRdtGroup{} | ||
if err := intelrdt.Set(helper.CgroupPath, helper.CgroupData.config); err != nil { | ||
t.Fatal(err) | ||
} | ||
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value, err := getCgroupParamUintHex(helper.CgroupPath, "intel_rdt.l3_cbm") | ||
if err != nil { | ||
t.Fatalf("Failed to parse intel_rdt.l3_cbm - %s", err) | ||
} | ||
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if value != l3CbmAfter { | ||
t.Fatal("Got the wrong value, set intel_rdt.l3_cbm failed.") | ||
} | ||
} | ||
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func TestIntelRdtStats(t *testing.T) { | ||
helper := NewCgroupTestUtil("intel_rdt", t) | ||
defer helper.cleanup() | ||
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const ( | ||
l3CbmContents = 0x1f00 | ||
) | ||
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helper.writeFileContents(map[string]string{ | ||
"intel_rdt.l3_cbm": strconv.FormatUint(l3CbmContents, 16), | ||
}) | ||
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intelrdt := &IntelRdtGroup{} | ||
stats := *cgroups.NewStats() | ||
if err := intelrdt.GetStats(helper.CgroupPath, &stats); err != nil { | ||
t.Fatal(err) | ||
} | ||
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if stats.IntelRdtStats.L3Cbm != l3CbmContents { | ||
t.Fatalf("Expected '0x%x', got '0x%x' for intel_rdt.l3_cbm", l3CbmContents, stats.IntelRdtStats.L3Cbm) | ||
} | ||
} |
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