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rockchip: add support for HINLINK OPC-H69K
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target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts
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| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
| // Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn> | ||
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| /dts-v1/; | ||
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89 changes: 89 additions & 0 deletions
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target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h69k.dts
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| @@ -0,0 +1,89 @@ | ||
| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
| // Copyright (c) 2023 AmadeusGhost <amadeus@jmu.edu.cn> | ||
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| /dts-v1/; | ||
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| #include "rk3568-hinlink-opc.dtsi" | ||
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| / { | ||
| model = "HINLINK OPC-H69K Board"; | ||
| compatible = "hinlink,opc-h69k", "rockchip,rk3568"; | ||
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| aliases { | ||
| ethernet0 = &gmac0; | ||
| ethernet1 = &gmac1; | ||
| }; | ||
| }; | ||
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| &cpu0_opp_table { | ||
| /delete-node/ opp-1608000000; | ||
| /delete-node/ opp-1800000000; | ||
| /delete-node/ opp-1992000000; | ||
| }; | ||
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| #ifdef DTS_NO_LEGACY | ||
| &gpu_opp_table { | ||
| /delete-node/ opp-700000000; | ||
| /delete-node/ opp-800000000; | ||
| }; | ||
| #endif | ||
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| &gmac0 { | ||
| assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; | ||
| assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; | ||
| assigned-clock-rates = <0>, <125000000>; | ||
| clock_in_out = "output"; | ||
| phy-mode = "rgmii-id"; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&gmac0_miim | ||
| &gmac0_tx_bus2 | ||
| &gmac0_rx_bus2 | ||
| &gmac0_rgmii_clk | ||
| &gmac0_rgmii_bus>; | ||
| snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; | ||
| snps,reset-active-low; | ||
| snps,reset-delays-us = <0 20000 100000>; | ||
| tx_delay = <0x3c>; | ||
| rx_delay = <0x2f>; | ||
| phy-handle = <&rgmii_phy0>; | ||
| status = "okay"; | ||
| }; | ||
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| &gmac1 { | ||
| assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; | ||
| assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; | ||
| assigned-clock-rates = <0>, <125000000>; | ||
| clock_in_out = "output"; | ||
| phy-mode = "rgmii-id"; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&gmac1m1_miim | ||
| &gmac1m1_tx_bus2 | ||
| &gmac1m1_rx_bus2 | ||
| &gmac1m1_rgmii_clk | ||
| &gmac1m1_rgmii_bus>; | ||
| snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; | ||
| snps,reset-active-low; | ||
| snps,reset-delays-us = <0 20000 100000>; | ||
| tx_delay = <0x4f>; | ||
| rx_delay = <0x26>; | ||
| phy-handle = <&rgmii_phy1>; | ||
| status = "okay"; | ||
| }; | ||
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| &mdio0 { | ||
| rgmii_phy0: ethernet-phy@0 { | ||
| compatible = "ethernet-phy-ieee802.3-c22"; | ||
| reg = <0x0>; | ||
| }; | ||
| }; | ||
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| &mdio1 { | ||
| rgmii_phy1: ethernet-phy@0 { | ||
| compatible = "ethernet-phy-ieee802.3-c22"; | ||
| reg = <0x0>; | ||
| }; | ||
| }; | ||
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| &vcc3v3_pcie { | ||
| gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; | ||
| }; |
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