An MLIR-based compiler framework bridges DSLs (domain-specific languages) to DSAs (domain-specific architectures).

Nuclei Microcontroller Software Interface Standard Development Repo

A posit arithmetic unit which implements Quire. Designed to be used both as a functional unit or as a tightly coupled accelerator.

OpenXuantie - OpenE906 Core

A matrix extension proposal for AI applications under RISC-V architecture

RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.

FlatBuffers: Memory Efficient Serialization Library

A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating custom functional units like posit arithmetic units.

Implementation of John L. Gustafson Unum Type III aka Posits using C++ Templates

This is an IDE for YSYX_NPC debuging

🤘 TT-NN operator library, and TT-Metalium low level kernel programming model.

Machine learning compiler based on MLIR for Sophgo TPU.

Open source high performance IEEE-754 floating unit

MiniCPM-V 2.6: A GPT-4V Level MLLM for Single Image, Multi Image and Video on Your Phone

Continuation of Clash Verge - A Clash Meta GUI based on Tauri (Windows, MacOS, Linux)

Chisel RISC-V Vector 1.0 Implementation

深度学习经典、新论文逐段精读

Rocket Chip Generator

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

Self checking RISC-V directed tests

Basic floating-point components for RISC-V processors

Flexible Intermediate Representation for RTL

Chisel: A Modern Hardware Design Language

使用Markdown制作和蒋炎岩老师幻灯片同一主题的Web幻灯片框架(Base on Reveal.js)

Complete NEMU based on RISC-V instruction set

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

PicoRV32 - A Size-Optimized RISC-V CPU