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coresight: etm4x: Cleanup TRCBBCTLR register accesses
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This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.

Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-15-james.clark@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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James-A-Clark authored and mathieupoirier committed Apr 13, 2022
1 parent 6619208 commit 67493ca
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Showing 2 changed files with 5 additions and 2 deletions.
4 changes: 2 additions & 2 deletions drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
Original file line number Diff line number Diff line change
Expand Up @@ -707,10 +707,10 @@ static ssize_t bb_ctrl_store(struct device *dev,
* individual range comparators. If include then at least 1
* range must be selected.
*/
if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0))
if ((val & TRCBBCTLR_MODE) && (FIELD_GET(TRCBBCTLR_RANGE_MASK, val) == 0))
return -EINVAL;

config->bb_ctrl = val & GENMASK(8, 0);
config->bb_ctrl = val & (TRCBBCTLR_MODE | TRCBBCTLR_RANGE_MASK);
return size;
}
static DEVICE_ATTR_RW(bb_ctrl);
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3 changes: 3 additions & 0 deletions drivers/hwtracing/coresight/coresight-etm4x.h
Original file line number Diff line number Diff line change
Expand Up @@ -220,6 +220,9 @@

#define TRCSSPCICRn_PC_MASK GENMASK(7, 0)

#define TRCBBCTLR_MODE BIT(8)
#define TRCBBCTLR_RANGE_MASK GENMASK(7, 0)

/*
* System instructions to access ETM registers.
* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
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