On-heterogeneous-computing

Heterogeneous Compiler

pytorch/glow code Compiler for Neural Network hardware accelerators

Design of the Glow Intermediate Representation code

google/jax code

Composable transformations of Python+NumPy programs: differentiate, vectorize, JIT to GPU/TPU, and more

Heterogeneous computing model

Amdahl's Law in the Multicore Era 10.1109/MC.2008.209 Hill and Marty

Roofline: an insightful visual performance model for multicore architectures

@article{williams2009roofline,
  title={Roofline: an insightful visual performance model for multicore architectures},
  author={Williams, Samuel and Waterman, Andrew and Patterson, David},
  journal={Communications of the ACM},
  volume={52},
  number={4},
  pages={65--76},
  year={2009},
  publisher={ACM}
}

Estimating and understanding architectural risk code

@inproceedings{cui2017estimating,
  title={Estimating and understanding architectural risk},
  author={Cui, Weilong and Sherwood, Timothy},
  booktitle={Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture},
  pages={651--664},
  year={2017},
  organization={ACM}
}

LogCA: A high-level performance model for hardware accelerators

@inproceedings{cui2017estimating,
  title={Estimating and understanding architectural risk},
  author={Cui, Weilong and Sherwood, Timothy},
  booktitle={Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture},
  pages={651--664},
  year={2017},
  organization={ACM}
}

Accelerator

A open source reimplementation of Google's Tensor Processing Unit (TPU). code

HL-HLS and HL-HDL

Plasticine A Reconfigurable Architecture For Parallel Patterns code

Chisel code

SpinalHDL code

Spatial: A Language and Compiler for Application Accelerators code

Flexible Intermediate Representation for RTL code

[paper] Reusability is FIRRTL Ground: Hardware Construction Languages, Compiler Frameworks, and Transformations

Yosys Open SYnthesis Suite code

##HLS Rapid Cycle-Accurate Simulator for High-Level Synthesis,FPGA'19