Pinned Loading

1. riscv-rtl-and-verification riscv-rtl-and-verification Public

   RV32I RISC-V core written in SystemVerilog, with an emphasis on coverage-driven verification using constrained-random stimulus, SVA assertions, and functional coverage

   SystemVerilog

2. ncurses-pacman ncurses-pacman Public

   Terminal-based Pac-Man game written in C++ using ncurses.

   C++ 3

3. fifo-and-uvm-testbench fifo-and-uvm-testbench Public

   SystemVerilog 1

4. ncurses-game-engine ncurses-game-engine Public

   A TUI game engine built using ncurses.

   C++

5. RISCV-core-in-systemverilog RISCV-core-in-systemverilog Public

   A riscv core implemented using systemverilog

   SystemVerilog 1

6. FPGA-Soc-Digital-Storage-Oscilloscope FPGA-Soc-Digital-Storage-Oscilloscope Public

   Verilog 1