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Merged
merged 2 commits into from
Nov 19, 2025
Merged

Added SPI TPM support for STM32H5 #622

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bdf337b
Added STM32H5 SPI Driver and support for TPM
dgarske Nov 14, 2025
b5d8958
Revert changes to cppcheck and unused arguments
dgarske Nov 18, 2025
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6 changes: 6 additions & 0 deletions .github/workflows/test-configs.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -320,6 +320,12 @@ jobs:
arch: arm
config-file: ./config/examples/stm32h5-tz.config

stm32h5_tz_tpm_test:
uses: ./.github/workflows/test-build.yml
with:
arch: arm
config-file: ./config/examples/stm32h5-tz-tpm.config

stm32h5_tz_dualbank_test:
uses: ./.github/workflows/test-build.yml
with:
Expand Down
1 change: 1 addition & 0 deletions Makefile
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Expand Up @@ -531,6 +531,7 @@ cppcheck:
cppcheck -f --enable=warning --enable=portability \
--suppress="ctunullpointer" --suppress="nullPointer" \
--suppress="objectIndex" --suppress="comparePointers" \
--check-level=exhaustive \
--error-exitcode=89 --std=c89 src/*.c hal/*.c hal/spi/*.c hal/uart/*.c

otp: tools/keytools/otp/otp-keystore-primer.bin FORCE
Expand Down
8 changes: 1 addition & 7 deletions arch.mk
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Expand Up @@ -101,7 +101,7 @@ ifeq ($(ARCH),AARCH64)
MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_c32.o
MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_arm64.o
endif
ifeq ($(NO_ARM_ASM),0)
ifneq ($(NO_ARM_ASM),1)
ARCH_FLAGS=-mstrict-align
CFLAGS+=$(ARCH_FLAGS) -DWOLFSSL_ARMASM -DWOLFSSL_ARMASM_INLINE -DWC_HASH_DATA_ALIGNMENT=8 -DWOLFSSL_AARCH64_PRIVILEGE_MODE
WOLFCRYPT_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/cpuid.o \
Expand Down Expand Up @@ -250,7 +250,6 @@ ifeq ($(ARCH),ARM)
WOLFBOOT_ORIGIN=0x10000000
ifeq ($(TZEN),1)
LSCRIPT_IN=hal/$(TARGET).ld
CFLAGS+=-DTZEN
else
LSCRIPT_IN=hal/$(TARGET)-ns.ld
endif
Expand Down Expand Up @@ -323,7 +322,6 @@ else
$(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/arm/thumb2-chacha-asm.o \
$(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/arm/thumb2-chacha-asm_c.o


CORTEXM_ARM_EXTRA_CFLAGS+=-DWOLFSSL_ARMASM -DWOLFSSL_ARMASM_NO_HW_CRYPTO \
-DWOLFSSL_ARMASM_NO_NEON -DWOLFSSL_ARMASM_THUMB2
endif
Expand Down Expand Up @@ -420,10 +418,6 @@ endif
endif
endif

ifeq ($(TZEN),1)
CFLAGS+=-DTZEN
endif


## Renesas RX
ifeq ($(ARCH),RENESAS_RX)
Expand Down
32 changes: 32 additions & 0 deletions config/examples/stm32h5-tz-tpm.config
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@@ -0,0 +1,32 @@
ARCH?=ARM
TZEN?=1
TARGET?=stm32h5
SIGN?=ECC256
HASH?=SHA256
DEBUG?=0
VTOR?=1
CORTEX_M0?=0
CORTEX_M33?=1
NO_ASM?=0
NO_MPU=1
EXT_FLASH?=0
SPI_FLASH?=0
ALLOW_DOWNGRADE?=0
NVM_FLASH_WRITEONCE?=1
WOLFBOOT_VERSION?=1
V?=0
SPMATH?=1
RAM_CODE?=1
DUALBANK_SWAP?=0
WOLFBOOT_PARTITION_SIZE?=0xA0000
WOLFBOOT_SECTOR_SIZE?=0x2000
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0C100000
WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0C1A0000
FLAGS_HOME=0
DISABLE_BACKUP=0
WOLFCRYPT_TZ=1
WOLFCRYPT_TZ_PKCS11=1
IMAGE_HEADER_SIZE?=1024
ARMORED=1
WOLFTPM=1
74 changes: 51 additions & 23 deletions hal/spi/spi_drv_stm32.c
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Expand Up @@ -83,6 +83,8 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,

/* Enable GPIO clock */
RCC_GPIO_CLOCK_ER |= (1 << base_num);
/* Delay after an RCC peripheral clock enabling */
reg = RCC_GPIO_CLOCK_ER;

/* Set Mode and Alternate Function */
reg = GPIO_MODE(base) & ~(0x03UL << (pin * 2));
Expand Down Expand Up @@ -112,6 +114,10 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,
/* configure output speed 0=low, 1=med, 2=high, 3=very high */
reg = GPIO_OSPD(base) & ~(0x03UL << (pin * 2));
GPIO_OSPD(base) |= (speed << (pin * 2));

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* TODO: Consider setting GPIO_SECCFGR(base) */
#endif
}

#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
Expand Down Expand Up @@ -369,24 +375,14 @@ int qspi_transfer(uint8_t fmode, const uint8_t cmd,
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
uint8_t RAMFUNCTION spi_read(void)
{
volatile uint32_t reg;
do {
reg = SPI1_SR;
} while(!(reg & SPI_SR_RX_NOTEMPTY));
return (uint8_t)SPI1_DR;
while (!(SPI1_SR & SPI_SR_RX_NOTEMPTY));
return SPI1_RXDR;
}

void RAMFUNCTION spi_write(const char byte)
{
int i;
volatile uint32_t reg;
do {
reg = SPI1_SR;
} while ((reg & SPI_SR_TX_EMPTY) == 0);
SPI1_DR = byte;
do {
reg = SPI1_SR;
} while ((reg & SPI_SR_TX_EMPTY) == 0);
while (!(SPI1_SR & SPI_SR_TX_EMPTY));
SPI1_TXDR = (uint8_t)byte;
}
#endif /* SPI_FLASH || WOLFBOOT_TPM */

Expand All @@ -398,7 +394,6 @@ void RAMFUNCTION spi_init(int polarity, int phase)

/* Setup clocks */
#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)

#ifdef TARGET_stm32u5
/* Clock configuration for QSPI defaults to SYSCLK
* (RM0456 section 11.8.47)
Expand All @@ -413,6 +408,10 @@ void RAMFUNCTION spi_init(int polarity, int phase)

#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
APB2_CLOCK_ER |= SPI1_APB2_CLOCK_ER_VAL;
#ifdef TARGET_stm32h5
RCC_CCIPR3 &= ~ (RCC_CCIPR3_SPI1SEL_MASK << RCC_CCIPR3_SPI1SEL_SHIFT);
RCC_CCIPR3 |= (0 << RCC_CCIPR3_SPI1SEL_SHIFT); /* PLL1_Q */
#endif
#endif

/* reset peripheral before setting up GPIO pins */
Expand Down Expand Up @@ -486,14 +485,39 @@ void RAMFUNCTION spi_init(int polarity, int phase)
#endif
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
/* Configure SPI1 for master mode */
# ifdef TARGET_stm32l0
SPI1_CR1 = SPI_CR1_MASTER | (polarity << 1) | (phase << 0);
# else
/* baud rate 5 (hclk/6) */
SPI1_CR1 = SPI_CR1_MASTER | (5 << 3) | (polarity << 1) | (phase << 0);
# endif
SPI1_CR1 &= ~SPI_CR1_SPI_EN;
#if defined(TARGET_stm32h5)
/* Clear any faults in the status register */
SPI1_IFCR = (SPI_IFCR_SUSPC | SPI_IFCR_MODFC | SPI_IFCR_TIFREC |
SPI_IFCR_OVRC | SPI_IFCR_UDRC);

/* baud rate 2 (hclk/8), data size (8-bits), CRC Size (8-bits),
* FIFO threshold level (1-data) */
SPI1_CFG1 = (
((2 & SPI_CFG1_BAUDRATE_MASK) << SPI_CFG1_BAUDRATE_SHIFT) |
((7 & SPI_CFG1_CRCSIZE_MASK) << SPI_CFG1_CRCSIZE_SHIFT) |
((0 & SPI_CFG1_FTHLV_MASK) << SPI_CFG1_FTHLV_SHIFT) |
((7 & SPI_CFG1_DSIZE_MASK) << SPI_CFG1_DSIZE_SHIFT));
SPI1_CFG2 = SPI_CFG2_MASTER | SPI_CFG2_SSOE |
(polarity << SPI_CFG2_CLOCK_POL_SHIFT) |
(phase << SPI_CFG2_CLOCK_PHASE_SHIFT);
#else
#ifndef TARGET_stm32l0 /* use existing/default baud for L0 */
/* Baud rate 5 (hclk/6), data size 8 bits */
SPI1_CR1 |= ((5 & SPI_CR1_BAUDRATE_MASK) << SPI_CR1_BAUDRATE_SHIFT);
#endif
SPI1_CR1 &= ~((1 << SPI_CR1_CLOCK_POL_SHIFT) | (1 << SPI_CR1_CLOCK_PHASE_SHIFT));
SPI1_CR1 |= SPI_CR1_MASTER |
(polarity << SPI_CR1_CLOCK_POL_SHIFT) |
(phase << SPI_CR1_CLOCK_PHASE_SHIFT);
SPI1_CR2 |= SPI_CR2_SSOE;
SPI1_CR1 |= SPI_CR1_SPI_EN;
#endif

SPI1_CR1 |= SPI_CR1_SPI_EN; /* Enable SPI */

#ifdef SPI_CR1_CSTART
SPI1_CR1 |= SPI_CR1_CSTART; /* use continuous start mode */
#endif
#endif /* SPI_FLASH || WOLFBOOOT_TPM */
}
}
Expand All @@ -505,8 +529,12 @@ void RAMFUNCTION spi_release(void)
}
if (initialized == 0) {
spi_reset();
#if defined (SPI_FLASH) || defined(WOLFBOOT_TPM)
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
#if defined(TARGET_stm32h5)
SPI1_CFG2 &= ~SPI_CFG2_SSOE;
#else
SPI1_CR2 &= ~SPI_CR2_SSOE;
#endif
SPI1_CR1 = 0;
#endif
stm_pins_release();
Expand Down
87 changes: 82 additions & 5 deletions hal/spi/spi_drv_stm32.h
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Expand Up @@ -29,7 +29,6 @@
#define GPIOC_BASE (0x40020800)
#define GPIOD_BASE (0x40020C00)
#define GPIOE_BASE (0x40021000)
#define GPIO_BASE GPIOA_BASE
#define SPI_GPIO GPIOB_BASE
#define SPI_CS_GPIO GPIOE_BASE
#define SPI_CS_FLASH 1 /* Flash CS connected to GPIOE1 */
Expand All @@ -40,6 +39,28 @@
#define SPI_MOSI_PIN 5 /* SPI_MOSI PB5 */
#endif /* TARGET_stm32f4 */


#ifdef TARGET_stm32h5
#include "hal/stm32h5.h"

#define APB2_CLOCK_RST RCC_APB2_CLOCK_RSTR
#define APB2_CLOCK_ER RCC_APB2_CLOCK_ER
#define RCC_GPIO_CLOCK_ER RCC_AHB2ENR_CLOCK_ER

/* Nucleo STM32H573ZI SPI_A Port (SPI1) */
#define SPI_CLOCK_PIO_BASE GPIOA_BASE
#define SPI_MISO_PIO_BASE GPIOG_BASE
#define SPI_MOSI_PIO_BASE GPIOB_BASE
#define SPI_CS_TPM_PIO_BASE GPIOD_BASE

#define SPI_PIN_AF 5 /* Alternate function for SPI pins */
#define SPI_CLOCK_PIN 5 /* SPI_SCK: PA5 */
#define SPI_MISO_PIN 9 /* SPI_MISO PG9 */
#define SPI_MOSI_PIN 5 /* SPI_MOSI PB5 */
#define SPI_CS_TPM 14 /* TPM CS connected to PD14 */
#endif /* TARGET_stm32h5 */


#ifdef TARGET_stm32u5

#ifdef TZEN
Expand Down Expand Up @@ -405,15 +426,67 @@

#define SPI1_APB2_CLOCK_ER_VAL (1 << 12)

#if defined(TARGET_stm32h5)
/* newer SPI/I2S peripheral */
#define SPI1_CR1 (*(volatile uint32_t *)(SPI1_BASE))
#define SPI1_CR2 (*(volatile uint32_t *)(SPI1_BASE + 0x04))
#define SPI1_CFG1 (*(volatile uint32_t *)(SPI1_BASE + 0x08))
#define SPI1_CFG2 (*(volatile uint32_t *)(SPI1_BASE + 0x0C))
#define SPI1_SR (*(volatile uint32_t *)(SPI1_BASE + 0x14))
#define SPI1_IFCR (*(volatile uint32_t *)(SPI1_BASE + 0x18))
#define SPI1_TXDR (*(volatile uint8_t *)(SPI1_BASE + 0x20))
#define SPI1_RXDR (*(volatile uint8_t *)(SPI1_BASE + 0x30))

#define SPI_CR1_SPI_EN (1 << 0)
#define SPI_CR1_MASRX (1 << 8) /* master automatic suspension in Receive mode */
#define SPI_CR1_CSTART (1 << 9) /* Continous start */
#define SPI_CR1_SSI (1 << 12) /* Internal slave select signal input level */
#define SPI_CFG1_DSIZE_MASK (0x1F)
#define SPI_CFG1_DSIZE_SHIFT (0)
#define SPI_CFG1_FTHLV_MASK (0x1F)
#define SPI_CFG1_FTHLV_SHIFT (5)
#define SPI_CFG1_CRCSIZE_MASK (0x1F)
#define SPI_CFG1_CRCSIZE_SHIFT (16)
#define SPI_CFG1_BAUDRATE_MASK (0x07)
#define SPI_CFG1_BAUDRATE_SHIFT (28)

#define SPI_CFG2_MASTER (1 << 22)
#define SPI_CFG2_LSBFIRST (1 << 23)
#define SPI_CFG2_CLOCK_PHASE_SHIFT (24)
#define SPI_CFG2_CLOCK_POL_SHIFT (25)
#define SPI_CFG2_SSM (1 << 26)
#define SPI_CFG2_SSOE (1 << 29)
#define SPI_CFG2_SSOM (1 << 30)
#define SPI_CFG2_AFCNTR (1 << 31) /* alternate function GPIOs control */
#define SPI_CFG2_COMM_MASK (0x3) /* 0=full duplex, 1=simplex tx, 2=simplex rx, 3=half duplex */
#define SPI_CFG2_COMM_SHIFT (17)

#define SPI_IFCR_SUSPC (1 << 11)
#define SPI_IFCR_MODFC (1 << 9)
#define SPI_IFCR_TIFREC (1 << 8)
#define SPI_IFCR_CRCEC (1 << 7)
#define SPI_IFCR_OVRC (1 << 6)
#define SPI_IFCR_UDRC (1 << 5)
#define SPI_IFCR_TXTFC (1 << 4)
#define SPI_IFCR_EOTC (1 << 3)

#define SPI_SR_RX_NOTEMPTY (1 << 0)
#define SPI_SR_TX_EMPTY (1 << 1)

#else

/* older SPI peripheral */
#define SPI1_CR1 (*(volatile uint32_t *)(SPI1_BASE))
#define SPI1_CR2 (*(volatile uint32_t *)(SPI1_BASE + 0x04))
#define SPI1_SR (*(volatile uint32_t *)(SPI1_BASE + 0x08))
#define SPI1_DR (*(volatile uint32_t *)(SPI1_BASE + 0x0c))
#define SPI1_TXDR (*(volatile uint8_t *)(SPI1_BASE + 0x0c))
#define SPI1_RXDR (*(volatile uint8_t *)(SPI1_BASE + 0x0c))

#define SPI_CR1_CLOCK_PHASE (1 << 0)
#define SPI_CR1_CLOCK_POLARITY (1 << 1)
#define SPI_CR1_CLOCK_PHASE_SHIFT (0)
#define SPI_CR1_CLOCK_POL_SHIFT (1)
#define SPI_CR1_MASTER (1 << 2)
#define SPI_CR1_BAUDRATE (0x07 << 3)
#define SPI_CR1_BAUDRATE_MASK (0x07)
#define SPI_CR1_BAUDRATE_SHIFT (3)
#define SPI_CR1_SPI_EN (1 << 6)
#define SPI_CR1_LSBFIRST (1 << 7)
#define SPI_CR1_SSI (1 << 8)
Expand All @@ -428,6 +501,7 @@
#define SPI_SR_TX_EMPTY (1 << 1)
#define SPI_SR_BUSY (1 << 7)

#endif

/* GPIO */
#define GPIO_MODE(base) (*(volatile uint32_t *)(base + 0x00)) /* GPIOx_MODER */
Expand All @@ -438,6 +512,9 @@
#define GPIO_BSRR(base) (*(volatile uint32_t *)(base + 0x18)) /* GPIOx_BSRR */
#define GPIO_AFL(base) (*(volatile uint32_t *)(base + 0x20)) /* GPIOx_AFRL */
#define GPIO_AFH(base) (*(volatile uint32_t *)(base + 0x24)) /* GPIOx_AFRH */
#ifndef GPIO_SECCFGR
#define GPIO_SECCFGR(base) (*(volatile uint32_t *)(base + 0x30)) /* GPIOx_SECCFGR */
#endif

#define GPIO_MODE_INPUT (0)
#define GPIO_MODE_OUTPUT (1)
Expand Down
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