Fixes for STM32H5 TrustZone and PKCS11 store

Makefile

@@ -384,6 +384,7 @@ keys: $(PRIVATE_KEY)
 
 clean:
 	$(Q)rm -f src/*.o hal/*.o hal/spi/*.o test-app/*.o src/x86/*.o
+	$(Q)rm -f src/wc_secure_calls.o
 	$(Q)rm -f $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/*.o $(WOLFBOOT_LIB_WOLFTPM)/src/*.o $(WOLFBOOT_LIB_WOLFTPM)/hal/*.o $(WOLFBOOT_LIB_WOLFTPM)/examples/pcr/*.o
 	$(Q)rm -f $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/Renesas/*.o
 	$(Q)rm -f wolfboot.bin wolfboot.elf wolfboot.map test-update.rom wolfboot.hex

arch.mk

@@ -1172,6 +1172,11 @@ WOLFCRYPT_OBJS+=$(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/logging.o
 # Debug UART
 ifeq ($(DEBUG_UART),1)
   CFLAGS+=-DDEBUG_UART
+
+  # If this target has a UART driver, add it to the OBJS
+  ifneq (,$(wildcard hal/uart/uart_drv_$(TARGET).c))
+    OBJS+=hal/uart/uart_drv_$(TARGET).o
+  endif
 endif
 
 ifeq ($(NXP_CUSTOM_DCD),1)

config/examples/stm32h5-dualbank.config

@@ -18,11 +18,12 @@ V?=0
 SPMATH?=1
 RAM_CODE?=0
 DUALBANK_SWAP?=1
-WOLFBOOT_PARTITION_SIZE?=0xC0000
+WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
-WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08040000
-WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x8140000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08160000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFFFFFF
 FLAGS_HOME=0
 DISABLE_BACKUP=0
 IMAGE_HEADER_SIZE?=1024
+ARMORED=1

config/examples/stm32h5-tz-dualbank-otp-lms.config

@@ -18,10 +18,10 @@ V?=0
 SPMATH?=1
 RAM_CODE?=1
 DUALBANK_SWAP?=1
-WOLFBOOT_PARTITION_SIZE?=0xC0000
+WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
-WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08040000
-WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x8140000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08160000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFFFFFF
 FLAGS_HOME=0
 DISABLE_BACKUP=0

config/examples/stm32h5-tz-dualbank-otp.config

@@ -18,10 +18,10 @@ V?=0
 SPMATH?=1
 RAM_CODE?=1
 DUALBANK_SWAP?=1
-WOLFBOOT_PARTITION_SIZE?=0xC0000
+WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
-WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08040000
-WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x8140000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08160000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFFFFFF
 FLAGS_HOME=0
 DISABLE_BACKUP=0

config/examples/stm32h5-tz.config

@@ -16,15 +16,16 @@ NVM_FLASH_WRITEONCE?=1
 WOLFBOOT_VERSION?=1
 V?=0
 SPMATH?=1
-RAM_CODE?=0
+RAM_CODE?=1
 DUALBANK_SWAP?=0
-WOLFBOOT_PARTITION_SIZE?=0xC0000
+WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
-WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08040000
-WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x8140000
-WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08010000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08100000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x081A0000
 FLAGS_HOME=0
 DISABLE_BACKUP=0
 WOLFCRYPT_TZ=1
 WOLFCRYPT_TZ_PKCS11=1
 IMAGE_HEADER_SIZE?=1024
+ARMORED=1

config/examples/stm32h5.config

@@ -18,11 +18,12 @@ V?=0
 SPMATH?=1
 RAM_CODE?=0
 DUALBANK_SWAP?=0
-WOLFBOOT_PARTITION_SIZE?=0xC0000
+WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
-WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08040000
-WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x8140000
-WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08010000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08100000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x081A0000
 FLAGS_HOME=0
 DISABLE_BACKUP=0
 IMAGE_HEADER_SIZE?=1024
+ARMORED=1

docs/Targets.md

@@ -885,6 +885,7 @@ arm-none-eabi-gdb
 (gdb) target remote:3333
 ```
 
+
 ## STM32H5
 
 Like [STM32L5](#stm32l5) and [STM32U5](#stm32u5), STM32H5 support is also demonstrated
@@ -902,8 +903,8 @@ For more information, see [/docs/flash-OTP.md](/docs/flash-OTP.md).
 The implementation shows how to switch from secure application to non-secure application,
 thanks to the system isolation performed, which splits the internal Flash and internal
 SRAM memories into two parts:
- - the first 256KB are used by wolfboot running in secure mode and the secure application
- - the remaining available space is used for non-secure application and update partition
+ - the first 384KB are used by wolfboot running in secure mode and the secure application
+ - the remaining available space (640KB) is used for non-secure application and update partition
 
 The example configuration for this scenario is available in [/config/examples/stm32h5.config](/config/examples/stm32h5.config).
 
@@ -913,14 +914,14 @@ The example configuration for this scenario is available in [/config/examples/st
 
 `STM32_Programmer_CLI -c port=swd -ob TZEN=0xB4`
 
-- set the option bytes to enable flash secure protection of first 256KB:
-`STM32_Programmer_CLI -c port=swd -ob SECWM1_PSTRT=0x0 SECWM1_PEND=0x1F SECWM2_PSTRT=0x1F SECWM2_PEND=0x0`
+- set the option bytes to enable flash secure protection of first 384KB and remainder as non-secure:
+`STM32_Programmer_CLI -c port=swd -ob SECWM1_PSTRT=0x0 SECWM1_PEND=0x2F SECWM2_PSTRT=0x2F SECWM2_PEND=0x0`
 
 - flash the wolfboot image to the secure partition:
 `STM32_Programmer_CLI -c port=swd -d wolfboot.bin 0x0C000000`
 
 - flash the application image to the non-secure partition:
-`STM32_Programmer_CLI -c port=swd -d test-app/image_v1_signed.bin 0x08040000`
+`STM32_Programmer_CLI -c port=swd -d test-app/image_v1_signed.bin 0x08060000`
 
 For a full list of all the option bytes tested with this configuration, refer to [STM32-TZ.md](/docs/STM32-TZ.md).
 
@@ -946,50 +947,55 @@ For DUALBANK with TrustZone use `stm32h5-tz-dualbank-otp.config`.
 
 DUALBANK configuration (Tested on NUCLEO-STM32H563ZI):
 
+```
 BANK A: 0x08000000 to 0x080FFFFFF (1MB)
 BANK B: 0x08100000 to 0x081FFFFFF (1MB)
+```
 
 First of all, ensure that the `SWAP_BANK` option byte is off when running wolfBoot
 for the first time:
-
-```
-STM32_Programmer_CLI -c port=swd -ob SWAP_BANK=0
-```
+`STM32_Programmer_CLI -c port=swd -ob SWAP_BANK=0`
 
 It is a good idea to start with an empty flash, by erasing all sectors via:
+`STM32_Programmer_CLI -c port=swd -e 0 255`
 
-```
-STM32_Programmer_CLI -c port=swd -e 0 255
-```
 Compile wolfBoot with `make`. The file `factory.bin` contains both wolfboot and the
 version 1 of the application, and can be uploaded to the board at the beginning
 of the first bank using `STM32_Programmer_CLI` tool:
-
-```
-STM32_Programmer_CLI -c port=swd -d factory.bin 0x08000000
-```
+`STM32_Programmer_CLI -c port=swd -d factory.bin 0x08000000`
 
 Optionally, you can upload another copy of wolfboot.bin to the beginning of the second bank.
-Wolfboot should take care of copying itself to the second bank upon first boot if you don't.:
-
-```
-STM32_Programmer_CLI -c port=swd -d wolfboot.bin 0x08100000
-```
+Wolfboot should take care of copying itself to the second bank upon first boot if you don't:
+`STM32_Programmer_CLI -c port=swd -d wolfboot.bin 0x08100000`
 
 After uploading the images, reboot your board. The green LED should indicate that v1 of the
 test application is running.
 
 To initiate an update, sign a new version of the app and upload the v3 to the update partition
 on the second bank:
 
-```
+```sh
 tools/keytools/sign --ecc256 test-app/image.bin wolfboot_signing_private_key.der 3
-STM32_Programmer_CLI -c port=swd -d test-app/image_v3_signed.bin 0x08110000
+STM32_Programmer_CLI -c port=swd -d test-app/image_v3_signed.bin 0x08160000
 ```
 
 Reboot the board to initiate an update via DUALBANK hw-assisted swap.
 Any version except the first one will also turn on the orange LED.
 
+### STM32H5 Debugging
+
+
+OpenOCD: `openocd -s /usr/local/share/openocd/scripts -f board/st_nucleo_h5.cfg`
+
+```sh
+arm-none-eabi-gdb
+source .gdbinit
+add-symbol-file test-app/image.elf 0x08060000
+mon reset init
+b main
+c
+```
+
 
 ## STM32H7
 

docs/flash-OTP.md

@@ -155,7 +155,7 @@ reboot : reboot the system
   - Sign a new version of the firmware: `./tools/keytools/sign --lms test-app/image.bin wolfboot_signing_private_key.der 2`
   - Run "update" command on the shell and wait for xmodem transfer
   - Use serial terminal that supports xmodem like "minicom" or "CoolTerm".
-    * Run `minicom` on `/dev/ttyACM0` and start file transfer using "CTRL+A; S"
+    * Run `minicom` on `/dev/ttyACM0` and start file transfer using "CTRL+A; S" -> `minicom -D /dev/ttyACM0 -b 115200`
     * Select xmodem then navigate to the new signed firmware file `test-app/image_v2_signed.bin`
   - During the transfer, the yellow LED will flash.
   - The green LED is dim because it's sync with the UART RX

hal/stm32_tz.c

@@ -213,31 +213,34 @@ void hal_tz_release_nonsecure_area(void)
 #define GTZC1_BASE             (0x50032400)
 #define GTZC1_TZSC             (*(volatile uint32_t *)(GTZC1_BASE + 0x00))
 #define GTZC1_TZIC             (*(volatile uint32_t *)(GTZC1_BASE + 0x0400))
-#define GTZC1_MPCBB1_S         ((volatile uint32_t *)(GTZC1_BASE + 0x0800 + 0x100))
-#define GTZC1_MPCBB2_S         ((volatile uint32_t *)(GTZC1_BASE + 0x0C00 + 0x100))
-#define GTZC1_MPCBB3_S         ((volatile uint32_t *)(GTZC1_BASE + 0x1000 + 0x100))
+#define GTZC1_MPCBB1_SECCFGR   ((volatile uint32_t *)(GTZC1_BASE + 0x0800 + 0x100))
+#define GTZC1_MPCBB2_SECCFGR   ((volatile uint32_t *)(GTZC1_BASE + 0x0C00 + 0x100))
+#define GTZC1_MPCBB3_SECCFGR   ((volatile uint32_t *)(GTZC1_BASE + 0x1000 + 0x100))
 
-#define SET_GTZC1_MPCBBx_S_VCTR(bank,n,val) \
-    (*((volatile uint32_t *)(GTZC1_MPCBB##bank##_S) + n ))= val
+#define SET_GTZC1_MPCBBx_SECCFGR_VCTR(bank,n,val) \
+    (*((volatile uint32_t *)(GTZC1_MPCBB##bank##_SECCFGR) + n )) = val
 
 void hal_gtzc_init(void)
 {
     int i;
-    /* One bit in the bitmask: 512B */
+    /* One bit in the bitmask: 512B
+     * 1: Secure access only to block
+     * 0: Non-secure access only to block
+     */
 
     /* Configure SRAM1 as secure (Low 256 KB) */
     for (i = 0; i < 16; i++) {
-        SET_GTZC1_MPCBBx_S_VCTR(1, i, 0xFFFFFFFF);
+        SET_GTZC1_MPCBBx_SECCFGR_VCTR(1, i, 0xFFFFFFFF);
     }
 
     /* Configure SRAM2 as secure (64 KB) */
     for (i = 0; i < 4; i++) {
-        SET_GTZC1_MPCBBx_S_VCTR(2, i, 0xFFFFFFFF);
+        SET_GTZC1_MPCBBx_SECCFGR_VCTR(2, i, 0xFFFFFFFF);
     }
 
     /* Configure SRAM3 as non-secure (320 KB) */
     for (i = 0; i < 20; i++) {
-        SET_GTZC1_MPCBBx_S_VCTR(3, i, 0x0);
+        SET_GTZC1_MPCBBx_SECCFGR_VCTR(3, i, 0x0);
     }
 }
 
@@ -288,7 +291,7 @@ void hal_tz_sau_init(void)
     /* SAU is set up before staging. Set up all areas as secure. */
 
     /* Non-secure callable: NSC functions area */
-    sau_init_region(0, 0x0C038000, 0x0C040000, 1);
+    sau_init_region(0, 0x0C040000, 0x0C05FFFF, 1);
 
     /* Secure: application flash area (first bank) */
     sau_init_region(1, WOLFBOOT_PARTITION_BOOT_ADDRESS, FLASH_BANK2_BASE - 1, 0);

hal/stm32h5.c

@@ -27,34 +27,46 @@
 #include "hal/stm32h5.h"
 #include "hal/armv8m_tz.h"
 
+#include "uart_drv.h"
+
 #define PLL_SRC_HSE 1
 
 #if TZ_SECURE()
 
 /* This function assumes that the boot and the update
  * partitions are at the same address in the two banks,
- * regardless wheather DUALBANK_SWAP is active or not.
+ * regardless if DUALBANK_SWAP is active or not.
  */
 static int is_flash_nonsecure(uint32_t address)
 {
-    uint32_t in_bank_offset = address & 0x000FFFFF;
-    if (in_bank_offset >= (WOLFBOOT_PARTITION_BOOT_ADDRESS - FLASHMEM_ADDRESS_SPACE))
+    uint32_t in_bank_offset = (address & 0x000FFFFF);
+    if (in_bank_offset >= (WOLFBOOT_PARTITION_BOOT_ADDRESS - FLASHMEM_ADDRESS_SPACE)) {
         return 1;
-    else
-        return 0;
+    }
+    return 0;
 }
 #endif
 
 
 static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
 {
     uint32_t reg = FLASH_ACR;
-    if ((reg & FLASH_ACR_LATENCY_MASK) < waitstates)
-        do {
-            FLASH_ACR =  (reg & ~(FLASH_ACR_LATENCY_MASK | (FLASH_ACR_WRHIGHFREQ_MASK << FLASH_ACR_WRHIGHFREQ_SHIFT))) |
-                         waitstates | (0x02 << FLASH_ACR_WRHIGHFREQ_SHIFT) ;
+    uint32_t wrhighfreq = 1; /* default flash signal delay */
+
+    if ((reg & FLASH_ACR_LATENCY_MASK) < waitstates) {
+        /* clear wrhighfreq and latency */
+        reg &= ~(FLASH_ACR_LATENCY_MASK |
+                (FLASH_ACR_WRHIGHFREQ_MASK << FLASH_ACR_WRHIGHFREQ_SHIFT));
+        if (waitstates > 3) { /* wait states 4 and 5 require = 2 */
+            wrhighfreq = 2;
         }
-        while ((FLASH_ACR & FLASH_ACR_LATENCY_MASK) != waitstates);
+        reg |= (waitstates | (wrhighfreq << FLASH_ACR_WRHIGHFREQ_SHIFT));
+        FLASH_ACR = reg;
+        ISB();
+        DMB();
+        /* wait for the register to be updated */
+        while (FLASH_ACR != reg);
+    }
 }
 
 void RAMFUNCTION hal_flash_wait_complete(uint8_t bank)
@@ -538,10 +550,15 @@ static void fork_bootloader(void)
 }
 #endif
 
-#include "uart_drv.h"
 void hal_init(void)
 {
     clock_pll_on();
+
+#ifdef DEBUG_UART
+    uart_init(115200, 8, 'N', 1);
+    uart_write("wolfBoot Init\n", 14);
+#endif
+
 #if TZ_SECURE()
     hal_gtzc_init();
     hal_tz_sau_init();