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1. cv32e40p cv32e40p Public

   Forked from openhwgroup/cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog

2. cv32e40p_verif cv32e40p_verif Public

   Forked from openhwgroup/core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly

3. chipyard chipyard Public

   Forked from ucb-bar/chipyard

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   C

4. asic_backend_design_sp22 asic_backend_design_sp22 Public

   Forked from iCloudX/asic_backend_design_sp22

   ASIC Back-end Design Flow

   Verilog

5. DAC-2020-Tutorial DAC-2020-Tutorial Public

   Forked from The-OpenROAD-Project/DAC-2020-Tutorial

   Material for OpenROAD Tutorial at DAC 2020

   Python

6. OpenLane OpenLane Public

   Forked from The-OpenROAD-Project/OpenLane

   OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

   Python