[WIP] My GW2A CPLD/FPGA/verilog playground
(TODO) how to use Gowin Programmer to combine fs files and bin files
- (x) Gowin_V1.9.8.11_Education_win.zip
- Gowin_V1.9.9Beta-4_Education_win.zip
- Gowin_V1.9.9_x64_win.zip
- nestang_install.7z/TangNano-20K-example-main_mod.7z
我实际测试过《从CPU到SoC的设计及实现》这本书中提到的高云IDE编译MIPS的单周期多周期流水线实现，
大概需要1.6K（或2.3K左右）个LUT逻辑单元，也就是说大部分高云开发板应该都能跑（虽然需要比较多的引脚）
- https://github.com/alangarf/apple-one
- apple1_on_anlogic
- https://gitee.com/pan-xingyu/apple1_on_anlogic
- https://www.bilibili.com/video/BV1db4y1p7jD/
实际用了一下高云的IDE综合器编译自己写（借鉴）的代码，
它和Quartus12基本上是一样的（不考虑什么针脚设计，
就简单的verilog和VHDL），除了VHDL语法会有一点细微的区别：
VHDL似乎遇到端口映射port map语句的时候会提示没有这个组件，
需要在实体名前面加上entity才不会出现语法错误，
但我查过书，其实不加entity也是对的
- https://www.waveshare.net/wiki/OpenEPM1270
- https://www.waveshare.net/w/upload/f/f7/EPM1270-Demo.7z
- Include LED sample verilog and VHDL code
- (dead) https://vanya.jp.net/td4/
- https://github.com/wuxx/TD4-4BIT-CPU/blob/master/software/test/test_0_output.s
- https://github.com/weimingtom/wmt_ai_study/blob/master/fpga_cpld_001.md
- https://github.com/asfdrwe/simpleTD4
- https://github.com/geodenx/td4
- https://github.com/myoan/td4
- https://github.com/zyu-c/verilog_TD4
- https://github.com/cielo-ee/TD4
- https://github.com/cielo-ee/td4_kai
- (dead) https://github.com/itoh5588/TD4-1
- https://github.com/ledyba/TD4_for_VerilogHDL
- https://github.com/oskimura/TD4
- https://github.com/Prokuma/TD4
- https://github.com/skylinker/td4_v1
- https://github.com/skylinker/td4_verilog
- (dead) https://github.com/t499/TD4
- https://github.com/thata/td4
- https://github.com/thata/td4_learning
- https://github.com/tiqwab/TD4
- https://github.com/varmil/td4-cpu-with-verilog
- CPU自制入门 ((日)水头一寿等)
search baidupan, CPUhomebrew-main.zip
search 620435 CPU自制入门.pdf
https://github.com/weimingtom/wmt_ai_study/blob/master/mcu_001.md - https://github.com/weimingtom/wmt_ai_study/blob/master/fpga_cpld_001.md