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[sram_ctrl,prim,rtl] Fix tlul_we -> ready timing path.
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This adds a new output to tlul_adapter_sram to signal when a
read-modify-write operation is pending. This is used in sram_ctrl to fix
a timing path that factored a tilelink write enable signal to a
tilelink ready signal.

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
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@GregAC
GregAC committed Apr 16, 2024
1 parent b745291 commit dc848b3
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Showing 18 changed files with 424 additions and 384 deletions.
19 changes: 10 additions & 9 deletions hw/dv/sv/sim_sram/sim_sram.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -71,15 +71,16 @@ module sim_sram #(
.tl_i(tl_in_i),
.tl_o(tl_in_o),

.req_o (sram_req),
.gnt_i (1'b1),
.we_o (sram_we),
.addr_o (sram_addr),
.wdata_o (sram_wdata),
.wmask_o (sram_wmask),
.rdata_i (sram_rdata),
.rvalid_i(sram_rvalid),
.rerror_i(2'b00)
.req_o (sram_req),
.gnt_i (1'b1),
.we_o (sram_we),
.addr_o (sram_addr),
.wdata_o (sram_wdata),
.wmask_o (sram_wmask),
.rdata_i (sram_rdata),
.rvalid_i (sram_rvalid),
.rerror_i (2'b00),
.rmw_in_progress_o()
);

prim_ram_1p #(
Expand Down
87 changes: 45 additions & 42 deletions hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -529,20 +529,21 @@ module flash_ctrl
) u_to_prog_fifo (
.clk_i,
.rst_ni,
.tl_i (prog_tl_h2d),
.tl_o (prog_tl_d2h),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (sw_wvalid),
.req_type_o (),
.gnt_i (sw_wready),
.we_o (),
.addr_o (),
.wmask_o (),
.intg_error_o(),
.wdata_o (sw_wdata),
.rdata_i ('0),
.rvalid_i (1'b0),
.rerror_i (2'b0)
.tl_i (prog_tl_h2d),
.tl_o (prog_tl_d2h),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (sw_wvalid),
.req_type_o (),
.gnt_i (sw_wready),
.we_o (),
.addr_o (),
.wmask_o (),
.intg_error_o (),
.wdata_o (sw_wdata),
.rdata_i ('0),
.rvalid_i (1'b0),
.rerror_i (2'b0),
.rmw_in_progress_o()
);

prim_fifo_sync #(
Expand Down Expand Up @@ -641,22 +642,23 @@ module flash_ctrl
) u_to_rd_fifo (
.clk_i,
.rst_ni,
.tl_i (tl_win_h2d[1]),
.tl_o (tl_win_d2h[1]),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (adapter_req),
.req_type_o (),
.tl_i (tl_win_h2d[1]),
.tl_o (tl_win_d2h[1]),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (adapter_req),
.req_type_o (),
// if there is no valid read operation, don't hang the
// bus, just let things normally return
.gnt_i (sw_rfifo_rvalid | rd_no_op_d),
.we_o (),
.addr_o (),
.wmask_o (),
.wdata_o (),
.intg_error_o(adapter_fifo_err),
.rdata_i (sw_rfifo_rdata),
.rvalid_i (adapter_rvalid | rd_no_op_q),
.rerror_i ({rd_no_op_q, 1'b0})
.gnt_i (sw_rfifo_rvalid | rd_no_op_d),
.we_o (),
.addr_o (),
.wmask_o (),
.wdata_o (),
.intg_error_o (adapter_fifo_err),
.rdata_i (sw_rfifo_rdata),
.rvalid_i (adapter_rvalid | rd_no_op_q),
.rerror_i ({rd_no_op_q, 1'b0}),
.rmw_in_progress_o()
);
assign sw_rfifo_wen = sw_sel & rd_ctrl_wen;
Expand Down Expand Up @@ -1300,20 +1302,21 @@ module flash_ctrl
) u_tl_adapter_eflash (
.clk_i,
.rst_ni,
.tl_i (gate_tl_h2d),
.tl_o (gate_tl_d2h),
.en_ifetch_i (flash_exec_en),
.req_o (flash_host_req),
.req_type_o (),
.gnt_i (flash_host_req_rdy),
.we_o (),
.addr_o (flash_host_addr),
.wdata_o (),
.wmask_o (),
.intg_error_o(eflash_cmd_intg_err),
.rdata_i (flash_host_rdata),
.rvalid_i (flash_host_req_done),
.rerror_i ({flash_host_rderr,1'b0})
.tl_i (gate_tl_h2d),
.tl_o (gate_tl_d2h),
.en_ifetch_i (flash_exec_en),
.req_o (flash_host_req),
.req_type_o (),
.gnt_i (flash_host_req_rdy),
.we_o (),
.addr_o (flash_host_addr),
.wdata_o (),
.wmask_o (),
.intg_error_o (eflash_cmd_intg_err),
.rdata_i (flash_host_rdata),
.rvalid_i (flash_host_req_done),
.rerror_i ({flash_host_rderr,1'b0}),
.rmw_in_progress_o()
);
flash_phy #(
Expand Down
87 changes: 45 additions & 42 deletions hw/ip/flash_ctrl/rtl/flash_ctrl.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -530,20 +530,21 @@ module flash_ctrl
) u_to_prog_fifo (
.clk_i,
.rst_ni,
.tl_i (prog_tl_h2d),
.tl_o (prog_tl_d2h),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (sw_wvalid),
.req_type_o (),
.gnt_i (sw_wready),
.we_o (),
.addr_o (),
.wmask_o (),
.intg_error_o(),
.wdata_o (sw_wdata),
.rdata_i ('0),
.rvalid_i (1'b0),
.rerror_i (2'b0)
.tl_i (prog_tl_h2d),
.tl_o (prog_tl_d2h),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (sw_wvalid),
.req_type_o (),
.gnt_i (sw_wready),
.we_o (),
.addr_o (),
.wmask_o (),
.intg_error_o (),
.wdata_o (sw_wdata),
.rdata_i ('0),
.rvalid_i (1'b0),
.rerror_i (2'b0),
.rmw_in_progress_o()
);

prim_fifo_sync #(
Expand Down Expand Up @@ -642,22 +643,23 @@ module flash_ctrl
) u_to_rd_fifo (
.clk_i,
.rst_ni,
.tl_i (tl_win_h2d[1]),
.tl_o (tl_win_d2h[1]),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (adapter_req),
.req_type_o (),
.tl_i (tl_win_h2d[1]),
.tl_o (tl_win_d2h[1]),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (adapter_req),
.req_type_o (),
// if there is no valid read operation, don't hang the
// bus, just let things normally return
.gnt_i (sw_rfifo_rvalid | rd_no_op_d),
.we_o (),
.addr_o (),
.wmask_o (),
.wdata_o (),
.intg_error_o(adapter_fifo_err),
.rdata_i (sw_rfifo_rdata),
.rvalid_i (adapter_rvalid | rd_no_op_q),
.rerror_i ({rd_no_op_q, 1'b0})
.gnt_i (sw_rfifo_rvalid | rd_no_op_d),
.we_o (),
.addr_o (),
.wmask_o (),
.wdata_o (),
.intg_error_o (adapter_fifo_err),
.rdata_i (sw_rfifo_rdata),
.rvalid_i (adapter_rvalid | rd_no_op_q),
.rerror_i ({rd_no_op_q, 1'b0}),
.rmw_in_progress_o()
);

assign sw_rfifo_wen = sw_sel & rd_ctrl_wen;
Expand Down Expand Up @@ -1301,20 +1303,21 @@ module flash_ctrl
) u_tl_adapter_eflash (
.clk_i,
.rst_ni,
.tl_i (gate_tl_h2d),
.tl_o (gate_tl_d2h),
.en_ifetch_i (flash_exec_en),
.req_o (flash_host_req),
.req_type_o (),
.gnt_i (flash_host_req_rdy),
.we_o (),
.addr_o (flash_host_addr),
.wdata_o (),
.wmask_o (),
.intg_error_o(eflash_cmd_intg_err),
.rdata_i (flash_host_rdata),
.rvalid_i (flash_host_req_done),
.rerror_i ({flash_host_rderr,1'b0})
.tl_i (gate_tl_h2d),
.tl_o (gate_tl_d2h),
.en_ifetch_i (flash_exec_en),
.req_o (flash_host_req),
.req_type_o (),
.gnt_i (flash_host_req_rdy),
.we_o (),
.addr_o (flash_host_addr),
.wdata_o (),
.wmask_o (),
.intg_error_o (eflash_cmd_intg_err),
.rdata_i (flash_host_rdata),
.rvalid_i (flash_host_req_done),
.rerror_i ({flash_host_rderr,1'b0}),
.rmw_in_progress_o()
);

flash_phy #(
Expand Down
29 changes: 15 additions & 14 deletions hw/ip/hmac/rtl/hmac.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -544,20 +544,21 @@ module hmac
) u_tlul_adapter (
.clk_i,
.rst_ni,
.tl_i (tl_win_h2d),
.tl_o (tl_win_d2h),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (msg_fifo_req ),
.req_type_o ( ),
.gnt_i (msg_fifo_gnt ),
.we_o (msg_fifo_we ),
.addr_o ( ), // Doesn't care the address other than sub-word
.wdata_o (msg_fifo_wdata ),
.wmask_o (msg_fifo_wmask ),
.intg_error_o( ),
.rdata_i (msg_fifo_rdata ),
.rvalid_i (msg_fifo_rvalid),
.rerror_i (msg_fifo_rerror)
.tl_i (tl_win_h2d),
.tl_o (tl_win_d2h),
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (msg_fifo_req ),
.req_type_o ( ),
.gnt_i (msg_fifo_gnt ),
.we_o (msg_fifo_we ),
.addr_o ( ), // Doesn't care the address other than sub-word
.wdata_o (msg_fifo_wdata ),
.wmask_o (msg_fifo_wmask ),
.intg_error_o ( ),
.rdata_i (msg_fifo_rdata ),
.rvalid_i (msg_fifo_rvalid),
.rerror_i (msg_fifo_rerror),
.rmw_in_progress_o()
);

// TL-UL to MSG_FIFO byte write handling
Expand Down
31 changes: 16 additions & 15 deletions hw/ip/kmac/rtl/kmac.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1002,21 +1002,22 @@ module kmac
) u_tlul_adapter_msgfifo (
.clk_i,
.rst_ni,
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.tl_i (tl_win_h2d[WinMsgFifo]),
.tl_o (tl_win_d2h[WinMsgFifo]),

.req_o (tlram_req),
.req_type_o (),
.gnt_i (tlram_gnt),
.we_o (tlram_we ),
.addr_o (tlram_addr),
.wdata_o (tlram_wdata),
.wmask_o (tlram_wmask),
.intg_error_o( ),
.rdata_i (tlram_rdata),
.rvalid_i (tlram_rvalid),
.rerror_i (tlram_rerror)
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.tl_i (tl_win_h2d[WinMsgFifo]),
.tl_o (tl_win_d2h[WinMsgFifo]),

.req_o (tlram_req),
.req_type_o (),
.gnt_i (tlram_gnt),
.we_o (tlram_we ),
.addr_o (tlram_addr),
.wdata_o (tlram_wdata),
.wmask_o (tlram_wmask),
.intg_error_o ( ),
.rdata_i (tlram_rdata),
.rvalid_i (tlram_rvalid),
.rerror_i (tlram_rerror),
.rmw_in_progress_o()
);

assign sw_msg_valid = tlram_req & tlram_we ;
Expand Down
25 changes: 13 additions & 12 deletions hw/ip/kmac/rtl/kmac_staterd.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,18 +64,19 @@ module kmac_staterd

.tl_i,
.tl_o,
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (tlram_req),
.req_type_o (),
.gnt_i (tlram_gnt),
.we_o (tlram_we ),
.addr_o (tlram_addr),
.wdata_o (unused_tlram_wdata),
.wmask_o (unused_tlram_wmask),
.intg_error_o(),
.rdata_i (tlram_rdata),
.rvalid_i (tlram_rvalid),
.rerror_i (tlram_rerror)
.en_ifetch_i (prim_mubi_pkg::MuBi4False),
.req_o (tlram_req),
.req_type_o (),
.gnt_i (tlram_gnt),
.we_o (tlram_we ),
.addr_o (tlram_addr),
.wdata_o (unused_tlram_wdata),
.wmask_o (unused_tlram_wmask),
.intg_error_o (),
.rdata_i (tlram_rdata),
.rvalid_i (tlram_rvalid),
.rerror_i (tlram_rerror),
.rmw_in_progress_o()
);

always_ff @(posedge clk_i or negedge rst_ni) begin
Expand Down
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